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PDF AD9230 Data sheet ( Hoja de datos )
| Número de pieza | AD9230 | |
| Descripción | 1.8 V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9230
FEATURES
SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.4 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = −79 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.3 LSB typical
INL = ±0.5 LSB typical
LVDS at 250 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
434 mW @ 250 MSPS—LVDS SDR mode
400 mW @ 250 MSPS—LVDS DDR mode
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9230 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9230 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
CML
VIN+
VIN–
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN
AGND
AVDD (1.8V)
REFERENCE
AD9230
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 12
12-BIT
CORE
SERIAL PORT
OUTPUT 12
STAGING
LVDS
RESET SCLK SDIO CSB
Figure 1. Functional Block Diagram
DRVDD
DRGND
D11 TO D0
OR+
OR–
DCO+
DCO–
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 434 mW @ 250 MSPS.
3. Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample and hold provide flexibility in system
design. Use of a single 1.8 V supply simplifies system
power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, disabling
the clock duty cycle stabilizer, power-down, gain adjust,
and output test pattern generation.
5. Pin-Compatible Family—10-bit pin-compatible family
offered as AD9211.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9230
AC SPECIFICATIONS1
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 2.
Parameter2
SNR
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
SINAD
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
WORST HARMONIC (Second or Third)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
WORST OTHER
(SFDR Excluding Second and Third)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
TWO-TONE IMD
140.2 MHz/141.3 MHz @ −7 dBFS
170.2 MHz/171.3 MHz @ −7 dBFS
ANALOG INPUT BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9230-170
Min Typ Max
63.8 64.6
63.5
63.5 64.3
63.3
63.5
63.0
63.7 64.5
63.4
63.3 64.1
63.1
63.3
61.8
10.6
10.5
10.4
10.1
−82 −78
−78
−78 −76
−75
−78
−68
−89 −84
−83
−89 −83
−83
−89
−80
73
700
AD9230-210
Min Typ Max
63.7 64.5
63.4
63.3 64.2
63.1
63.4
61.5
63.6 64.4
63.4
63.2 64.0
63.0
63.1
61.1
10.6
10.5
10.4
10.0
−86 −80
−78
−80 −77
−75
−79
−70
−89 −84
−83
−86 −81
−81
−79
−79
75
67
700
AD9230-250
Min Typ Max
63.3 64.1
62.5
63.0 63.9
62.3
63.3
63.3
63.3 64.0
62.4
62.9 63.7
62.2
63.0
62.8
10.5
10.4
10.3
10.3
−84 −79
−76
−79 −76
−75
−78
−75
−84 −79
−76
−83 −79
−75
−83
−80
78
73
700
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
3 140 MHz for the AD9230-170 speed grade, 170 MHz for the AD9230-210 and AD9230-250 speed grades.
Rev. 0 | Page 4 of 32
5 Page 
AD9230
Pin No.
5
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Mnemonic
D5−
D5+
D6−
D6+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
OR−
OR+
Description
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit (MSB).
D11 True Output Bit (MSB).
Overrange Complement Output Bit.
Overrange True Output Bit.
1 AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9230.PDF ] | |
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