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PDF ADS8413 Data sheet ( Hoja de datos )
| Número de pieza | ADS8413 | |
| Descripción | SAR ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown | |
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BurrĆBrown Products
from Texas Instruments
ADS8413
16-BIT, 2-MSPS, LVDS SERIAL INTERFACE,
SAR ANALOG-TO-DIGITAL CONVERTER
SLAS490 – OCTOBER 2005
FEATURES
• 2-MHz Sample Rate
• 16-Bit Resolution
• SNR 92 dB at 10 kHz I/P
• THD –107 dB at 10 kHz I/P
• ±1 LSB Typ, ±2 LSB INL Max
• +0.7/–0.5 LSB Typ, +1.5/–1 LSB DNL Max
• Unipolar Differential Input Range: –4 V
to 4 V
• Internal Reference
• Internal Reference Buffer
• 200-Mbps LVDS Serial Interface
• Optional 200-MHz Internal Interface Clock
• 16-/8-Bit Data Frame
• Zero Latency at Full Speed
• Power Dissipation: 290 mW at 2 MSPS
• Nap Mode (125 mW Power Dissipation)
• Power Down (5 µW)
• 48-Pin QFN Package
APPLICATIONS
• Medical Instrumentation
• HIgh-Speed Data Acquisiton Systems
• High-Speed Close-Loop Systems
• Communication
DESCRIPTION
The ADS8413 is a 16-bit, 2-MSPS, analog-to-digital
(A/D) converter with 4-V internal reference. The
device includes a capacitor based SAR A/D converter
with inherent sample and hold.
The ADS8413 also includes a 200-Mbps, LVDS,
serial interface. This interface is designed to support
daisy chaining or cascading of multiple devices. A
selectable 16-/8-bit data frame mode enables the use
of a single shift register chip (SN65LVDS152) for
converting the data to parallel format.
The ADS8413 unipolar differential input range
supports a differential input swing of –Vref to +Vref with
a common-mode voltage of +Vref/2.
The nap feature provides substantial power saving
when used at lower conversion rates.
The ADS8413 is available in a 48-pin QFN package.
Type/Speed
18-Bit Pseudo-Diff
500 kHz
ADS8383
18-Bit Pseudo-Bipolar, Fully Diff
16-Bit Pseudo-Diff
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
High-Speed SAR Converter Family
~ 600 kHz
ADS8381
ADS8380 (S)
ADS8382 (S)
750 kHZ
ADS8370 (S) ADS8371
ADS8372 (S)
1 MHz
1.25 MHz
2 MHz
ADS8401/05
ADS8411
ADS8410
(S-LVDS)
ADS8402/06
ADS8412
ADS8413
(S-LVDS)
ADS7890 (S)
3 MHz
ADS7891
4 MHz
ADS7881
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
1 page  
ADS8413
www.ti.com
SLAS490 – OCTOBER 2005
SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
RECEIVER
VITH+
VITH-
VIC
CI
Positive going differential voltage threshold
Negative going differential voltage threshold
Common mode input voltage
Input capacitance
–50
0.2 1.2
5
50
2.2
UNIT
mV
V
pF
TIMING REQUIREMENTS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted)
PARAMETER
SAMPLING AND CONVERSION RELATED
MIN
tacq Acquisition time
100
tcnv Conversion time
tw1 Pulse duration, CONVST high
tw2 Pulse duration, CONVST low
td1 Delay time, CONVST rising edge to sample start
td2 Delay time, CONVST falling edge to conversion start
td3 Delay time, CONVST falling edge to busy high
td4 Delay time, conversion end to busy low
tw3 Pulse duration, CSTART high
100
40
+VBD = 3.3 V
+VBD = 5 V
+VBD = 3.3 V
+VBD = 5 V
100
tw4 Pulse duration, CSTART low
45
td5 Delay time, CSTART rising edge to sample start
td6 Delay time, CSTART falling edge to conversion start
td7 Delay time, CSTART falling edge to busy high
+VBD = 3.3 V
+VBD = 5 V
I/O RELATED
td8 Delay time, RD falling edge while CS low to BUS_BUSY high
td9
Delay time, RD falling edge while CS low to SYNC_O and SDO out of +VBD = 3.3 V
3-state condition (for device with LAT_Y/N pulled low)
+VBD = 5 V
td10
Delay time, pre_conversion end (point A) to SYNC_O and SDO out of 3-state
condition
td11 Delay time, pre_conversion end (point A) to BUS_BUSY high
VBD = 3.3 V
+VBD = 5 V
td12 Delay time, conversion phase end to SYNC_O high
td13 Delay time, RD falling edge while CS low to SYNC_O high
+VBD = 3.3 V
+VBD = 5 V
tw5 Pulse duration, RD low for device in no latency mode
td14 Delay time, CLK_O rising edge to data valid
+VBD = 3.3 V
+VBD = 5 V
td15
Delay time, BUS_BUSY low to SYNC_O high in daisy chain mode
indicating receiving device to output the data
+VBD = 3.3 V
+VBD = 5 V
6
5.5 + 4*tCLK
5 + 4*tCLK
5
4*tCLK– 6.5
4*tCLK– 6
TYP
MAX UNIT
REF
ns
391 ns
ns
ns
5 ns
5 ns
14
ns
13
8
ns
7
ns
ns
7.5 ns
7.5 ns
16.5
15.5
ns
Figure 1,
Figure 2
Figure 1,
Figure 2
Figure 1
Figure 1,
Figure 2
Figure 1
Figure 1,
Figure 2
Figure 1,
Figure 2
Figure 1,
Figure 2
Figure 1,
Table 2
Figure 1,
Figure 2,
Table 2
Figure 1,
Table 2
Figure 1,
Figure 2,
Table 2
Figure 1,
Figure 2,
Table 2
16
29
28
22
8
7
9 + tCLK
8.5 + 5*tCLK
8 + 5*tCLK
1.4
1.3
4*tCLK– 3
4*tCLK– 2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5
Figure 5
Figure 6
Figure 6
Figure 6
Figure 5
Figure 11
Figure 5,
Figure 6
Figure 7,
Figure 12
5
5 Page 
www.ti.com
RD
SYNC_O
CLK_O
1F 1R
2R
See Figures 5 and 6
See Figures 7 and 8
SDO
BUS BUSY
D15 D14
ADS8413
SLAS490 – OCTOBER 2005
18F 18R
D0
Figure 3. Data Read With CS Low and BYTE = 0
As shown in Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is
in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets
BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge)
if BYTE i/p is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O
falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is
latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th
rising edge (18R, or the second rising edge after a SYNC_O rising edge).
CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the
next data read cycle.
DATA READ IN BYTE MODE
Byte mode is selected by setting BYTE = 1, this mode is allowed for any condition listed in Table 1. Figure 4
shows a data read operation in byte mode.
RD
SYNC_O
CLK_O
1F 1R
2R
9F 9R
10R
18F 18R
SDO
BUS BUSY
D15 D14
D8 D7
D0
Figure 4. Data Read Timing Diagram with CS Low and BYTE = 1
Similar to Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and device is in a
wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY
high at the start of the read cycle. The SYNC_O cycle is 8 clocks wide (rising edge to rising edge) if BYTE i/p is
held high and can be used to synchronize a data frame. The clock count begins with the first CLK_O falling edge
after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each subsequent data
bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling edges of clock. The
next rising edge of SYNC_O coincides with the 8th rising edge of the clock. D8 is latched out on the 9th rising
edge of the clock. The receiver can latch the de-serialized higher byte on the 10th rising edge (10R, or second
rising edge after a SYNC_O rising edge). The de-serialized lower byte can be latched on the 18th rising edge
(18R).
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADS8413.PDF ] | |
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