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PDF PCM1808 Data sheet ( Hoja de datos )
| Número de pieza | PCM1808 | |
| Descripción | STEREO A/D CONVERTER | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PCM1808 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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BurrĆBrown Products
from Texas Instruments
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
FEATURES
• 24-Bit Delta-Sigma Stereo A/D Converter
• Single-Ended Voltage Input: 3 Vp-p
• High Performance:
– THD + N: –93 dB (Typical)
– SNR: 99 dB (Typical)
– Dynamic Range: 99 dB (Typical)
• Oversampling Decimation Filter:
– Oversampling Frequency: ×64
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
• Flexible PCM Audio Interface
– Master/Slave Mode Selectable
– Data Formats: 24-Bit I2S, 24-Bit
Left-Justified
• Power Down and Reset by Halting System
Clock
• Analog Antialias LPF Included
• Sampling Rate: 8 kHz–96 kHz
• System Clock: 256 fS, 384 fS, 512 fS
• Dual Power Supplies:
– 5-V for Analog
– 3.3-V for Digital
• Package: 14-Pin TSSOP
APPLICATIONS
• DVD Recorder
• Digital TV
• AV Amplifier/Receiver
• MD Player
• CD Recorder
• Multitrack Receiver
• Electric Musical Instrument
DESCRIPTION
The PCM1808 is high-performance, low-cost,
single-chip, stereo analog-to-digital converter with
single-ended analog voltage input. The PCM1808
uses a delta-sigma modulator with 64-times
oversampling and includes a digital decimation filter
and high-pass filter that removes the dc component
of the input signal. For various applications, the
PCM1808 supports master and slave mode and two
data formats in serial audio interface.
The PCM1808 supports the power-down and reset
function by means of halting the system clock.
The PCM1808 is suitable for wide variety of
cost-sensitive consumer applications where good
performance and operation with a 5-V analog supply
and 3.3-V digital supply is required. The PCM1808 is
fabricated using a highly advanced CMOS process
and is available in a small, 14-pin TSSOP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
1 page  
PCM1808
www.ti.com
PIN ASSIGNMENTS
PW PACKAGE
(TOP VIEW)
SLES177A – APRIL 2006 – REVISED AUGUST 2006
VREF
AGND
VCC
VDD
DGND
SCKI
LRCK
1
2
3
4
5
6
7
14 VINR
13 VINL
12 FMT
11 MD1
10 MD0
9 DOUT
8 BCK
P0032-02
TERMINAL FUNCTIONS
TERMINAL
NAME
PIN
AGND
2
BCK
8
DGND
5
DOUT
9
FMT
12
LRCK
7
MD0
10
MD1
11
SCKI
6
VCC
VDD
VINL
VINR
VREF
3
4
13
14
1
I/O DESCRIPTION
– Analog GND
I/O Audio data bit clock input/output (1)
– Digital GND
O Audio data digital output
I Audio interface format select (2)
I/O Audio data latch enable input/output (1)
I Audio interface mode select 0 (2)
I Audio interface mode select 1 (2)
I System clock input; 256 fS, 384 fS or 512 fS(3)
– Analog power supply, 5-V
– Digital power supply, 3.3-V
I Analog input, L-channel
I Analog input, R-channel
– Reference voltage decoupling (= 0.5 VCC)
(1) Schmitt-trigger input with internal pulldown (50-kΩ, typical)
(2) Schmitt-trigger input with internal pulldown (50-kΩ, typical), 5-V tolerant
(3) Schmitt-trigger input, 5-V tolerant
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PCM1808
www.ti.com
SLES177A – APRIL 2006 – REVISED AUGUST 2006
SYSTEM CLOCK
The PCM1808 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency.
The system clock must be supplied on SCKI (pin 6).
The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating
at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, the system clock frequency must be controlled
through the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is divided down
automatically to generate frequencies of 128 fS and 64 fS, which are used to operate the digital filter and the
delta-sigma modulator, respectively.
Table 1 shows some typical relationships between sampling frequency and system clock frequency, and
Figure 17 shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING FREQUENCY (kHz)
8
16
32
44.1
48
64
88.2
96
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
256 fS
384 fS
512 fS
2.048
3.072
4.096
4.096
6.144
8.192
8.192
12.288
16.384
11.2896
16.9344
22.5792
12.288
18.432
24.576
16.384
24.576
32.768
22.5792
33.8688
45.1584
24.576
36.864
49.152
SCKI
SYMBOL
tw(SCKH)
tw(SCKL)
tw(SCKH)
tw(SCKL)
SCKI
2V
PARAMETER
System clock pulse duration, HIGH
System clock pulse duration, LOW
System clock duty cycle
MIN
8
8
40%
Figure 17. System Clock Timing
0.8 V
T0005B07
MAX
60%
UNIT
ns
ns
FADE-IN AND FADE-OUT FUNCTIONS
The PCM1808 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions come
into operation in some cases as described in several following sections. The level changes from 0 dB to mute or
mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection.
Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input
frequency (fin). It takes 48/fin until processing is completed. If there is no zero cross during 8192/fS, DOUT is
faded in or out by force during 48/fS (TIME OUT). Figure 18 illustrates the fade-in and fade-out operation
processing.
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11
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet PCM1808.PDF ] | |
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