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PDF ADIS16250 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16250 | |
| Descripción | Programmable Low Power Gyroscope | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Programmable Low Power Gyroscope
ADIS16250
FEATURES
Yaw rate gyro with digital range scaling
±80°/sec, ±160°/sec, and ±320°/sec settings
14-bit digital gyroscope sensor outputs
12-bit digital temperature sensor output
Calibrated sensitivity and bias
Single-command bias calibration
Digitally controlled sample rate
Digitally controlled frequency response
Dual alarm settings with rate/threshold limits
Embedded integration for short-term angle estimates
Digitally activated self-test
Digitally activated low power mode
Interrupt-driven wake-up
SPI®-compatible serial interface
50 Hz sensor bandwidth
Auxiliary 12-bit ADC input and 12-bit DAC output
Auxiliary digital input/output
Single-supply operation: 4.75 V to 5.25 V
2000 g powered shock survivability
APPLICATIONS
Instrumentation control
Platform control and stabilization
Motion control and analysis
Avionics instrumentation
Navigation
Image stabilization
Robotics
GENERAL DESCRIPTION
The ADIS16250 is a complete, angular rate measurement
system available in a single compact package enabled by Analog
Devices, Inc., iSensor™ integration. By enhancing Analog
Devices iMEMS® sensor technology with an embedded signal
processing solution, the ADIS16250 provides factory calibrated
and tunable digital sensor data in a convenient format that can
be accessed using a simple SPI serial interface. The SPI interface
provides access to measurements for the gyroscope, temperature,
power supply, and one auxiliary analog input. Easy access to
calibrated digital sensor data provides developers with a system-
ready device, reducing development time, cost, and program risk.
The device range can be digitally selected from three different
settings: ±80°/sec, ±160°/sec, and ±320°/sec. Unique
characteristics of the end system are accommodated easily
RATE
FILT
VCC
COM
FUNCTIONAL BLOCK DIAGRAM
AUX AUX
ADC DAC VREF
TEMPERATURE
SENSOR
ADIS16250
GYROSCOPE
SENSOR
SELF-TEST
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
DIGITAL
CONTROL
SPI
PORT
CS
SCLK
DIN
DOUT
POWER
MANAGEMENT
ALARM
AUXILIARY
I/O
RST
Figure 1.
DIO0 DIO1
through several built-in features, including a single-command
auto-zero recalibration function, as well as configurable sample
rate and frequency response. Additional features can be used to
further reduce system complexity, including:
• Configurable alarm function
• Auxiliary 12-bit ADC and DAC
• Two configurable digital I/O ports
• Digital self-test function
System power dissipation can be optimized via the ADIS16250
power management features, including an interrupt-driven wake-up.
The ADIS16250 is available in an 11 mm × 11 mm × 5.5 mm,
laminate-based land grid array (LGA) package with a
temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tDATARATE
tDATARATE
tCSHIGH
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Description
Fast mode2
Normal mode2
Chip select period, fast mode2
Chip select period, normal mode2
Chip select high
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
1 Guaranteed by design; typical specifications are not tested or guaranteed.
2 Based on sample rate selection.
tDATA RATE
CS
SCLK
Figure 2. SPI Chip Select Timing
Min1
0.01
0.01
40
100
1/fSCLK
48.8
24.4
48.8
5
ADIS16250
Typ
Max1
Unit
2.5 MHz
1.0 MHz
μs
μs
ns
100 ns
ns
ns
5 12.5 ns min
5 12.5 ns min
ns typ
CS
SCLK
DOUT
DIN
tCS
1
MSB
W/R
23 4 5 6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5 A4 A3 A2
15 16
tSFS
DB2 DB1 LSB
D2 D1 LSB
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. 0 | Page 5 of 20
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BASIC OPERATION
The ADIS16250 is designed for simple integration into
industrial system designs, requiring only a 5.0 V power supply
and a four-wire, industry standard serial peripheral interface (SPI).
All outputs and user-programmable functions are handled by
a simple register structure. Each register is 16 bits in length and
has its own unique bit map. The 16 bits in each register consist
of an upper (D8 to D15) byte and a lower (D0 to D7) byte, each
of which has its own 6-bit address.
SERIAL PERIPHERAL INTERFACE (SPI)
The ADIS16250 serial peripheral interface (SPI) port includes
four signals: chip select (CS), serial clock (SCLK), data input
(DIN), and data output (DOUT). The CS line enables the
ADIS16250 SPI port and frames each SPI event. When this
signal is high, the DOUT lines are in a high impedance state
and the signals on DIN and SCLK have no impact on operation.
A complete data frame contains 16 clock cycles. Because the SPI
port operates in full duplex mode, it supports simultaneous,
16-bit receive (DIN) and transmit (DOUT) functions during the
same data frame.
Refer to Table 2, Figure 2, and Figure 3 for detailed timing and
operation of the SPI port.
ADIS16250
Writing to Registers
Figure 20 displays a typical data frame for writing a command
to a control register. In this case, the first bit of the DIN
sequence is a 1, followed by a 0, the 6-bit address, and
the 8-bit data command. Because each write command covers
a single byte of data, two data frames are required when writing
the entire 16-bit space of a register.
Reading from Registers
Reading the contents of a register requires a modification to the
sequence in Figure 20. In this case, the first two bits in the DIN
sequence are 0, followed by the address of the register. Each register
has two addresses (upper, lower), but either one can be used to
access its entire 16 bits of data. The final 8 bits of the DIN sequence
are irrelevant and can be counted as “don’t cares” during a read
command. During the next data frame, the DOUT sequence
contains the register’s 16-bit data, as shown in Figure 21.
Although a single read command requires two separate data
frames, the full duplex mode minimizes this overhead, requiring
only one extra data frame when continuously sampling.
CS
SCLK
DIN W/R
DATA FRAME
A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
WRITE = 1
READ = 0
CS
REGISTER ADDRESS
DATA FOR WRITE COMMANDS
DON’T CARE FOR READ COMMANDS
Figure 20. DIN Bit Sequence
DATA FRAME
DATA FRAME
SCLK
DIN
W/R BIT
DOUT
ADDRESS
ZERO
DON’T CARE
NEXT COMMAND
BASED ON PREVIOUS COMMAND
16-BIT REGISTER CONTENTS
Figure 21. SPI Sequence for Read Commands
Rev. 0 | Page 11 of 20
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADIS16250.PDF ] | |
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