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PDF AD7612 Data sheet ( Hoja de datos )
| Número de pieza | AD7612 | |
| Descripción | 16-bit charge redistribution successive approximation register | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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16-Bit, 750 kSPS, Unipolar/Bipolar
Programmable Input PulSAR® ADC
AD7612
FEATURES
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput
750 kSPS (warp mode)
600 kSPS (normal mode)
500 kSPS (impulse mode)
INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR)
16-bit resolution with no missing codes
SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz
THD: −107 dB typical
iCMOS™ process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation: 190 mW @ 750 kSPS
Pb-free, 48-lead LQFP and LFCSP (7 mm × 7 mm) packages
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7612 is a 16-bit charge redistribution successive
approximation register (SAR), architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write only serial configuration port for input
range and operating mode. The AD7612 contains a high speed
16-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on CNVST
samples the analog input on IN+ with respect to a ground
sense, IN−. The AD7612 features four different analog input
ranges and three different sampling modes: warp mode for the
fastest throughput, normal mode for the fastest asynchronous
throughput, and impulse mode where power consumption is
scaled linearly with throughput. Operation is specified from
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND
AGND
AVDD
PDREF
PDBUF
IN+
IN–
REF
REF
AMP
SWITCHED
CAP DAC
CNVST
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
AD7612
SERIAL DATA
PORT
SERIAL
CONFIGURATION
PORT
16
PARALLEL
INTERFACE
OVDD
OGND
D[15:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
RD
CS
WARP IMPULSE BIPOLAR TEN
Figure 1.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
100 kSPS to 500 kSPS to 800 kSPS to
250 kSPS
570 kSPS
1000 kSPS
Pseudo
Differential
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
True Bipolar AD7663
AD7665
AD7612
AD7671
True
Differential
AD7675
AD7676
AD7677
18-Bit, True
Differential
Multichannel/
Simultaneous
AD7678
AD7679
AD7654
AD7655
AD7674
>1000
kSPS
AD7621
AD7622
AD7623
AD7641
AD7643
PRODUCT HIGHLIGHTS
1. Programmable input range and mode selection.
Pins or serial port for selecting input range/mode select.
2. Fast throughput.
In warp mode, the AD7612 is 750 kSPS.
3. Superior Linearity.
No missing 16-bit code. ±1.5 LSB max INL.
4. Internal Reference.
5 V internal reference with a typical drift of ±3 ppm/°C
and an on-chip temperature sensor.
5. Serial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 3.3 V or 5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD7612
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time
Warp Mode/Normal Mode/Impulse Mode
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
Warp Mode/Normal Mode/Impulse Mode
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC HI-Z
CS High to Internal SDCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
Symbol Min
Typ
Max Unit
t1 10
t2
1.33/1.67/2
t3
t4
t5
t6 10
t7
2
t8
380
t9 10
ns
μs
35 ns
950/1250/1450 ns
ns
ns
950/1250/1450 ns
ns
ns
t10
t11 20
t12
t13 2
910/1160/1410
40
15
ns
ns
ns
ns
t14
t15
t16
t17
t18 3
t19 30
t20 15
t21 10
t22 4
t23 5
t24 5
t25
t26
t27
t28
65/315/560
10
10
10
45
See Table 4
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t29
830/1070/1310
ns
t30 25
ns
Rev. 0 | Page 5 of 32
5 Page 
AD7612
Pin No.
43
45
46
Mnemonic
IN+
TEMP
REFBUFIN
47 PDREF
48 PDBUF
Type1
AI
AO
AI
DI
DI
Description
Analog Input. Referenced to IN−.
Temperature Sensor Analog Output.
Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF =
low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference
Input section.
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2 In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet AD7612.PDF ] | |
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