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IDT74ALVCH16823 fiches techniques PDF

Integrated Device Technology - 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP

Numéro de référence IDT74ALVCH16823
Description 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT74ALVCH16823 fiche technique
IDT74ALVCH16823
3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
3.3V CMOS 18-BIT
BUS-INTERFACE FLIP-
FLOP WITH 3-STATE OUT-
PUTS AND BUS-HOLD
INDUSTRwIAwLwT.EDMaPtaESRhAeTeUt4RUE.cRoAmNGE
IDT74ALVCH16823
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS
technology.TheALVCH16823features3-stateoutputsdesigned specifically
for driving highly capacitive or relatively low-impedance loads. The device is
particularly suitable for implementing wider buffer registers, I/O ports, bidirec-
tional bus drivers with parity, and working registers.
The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.
With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the
low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer,
thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs
to go low independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs
in either a normal logic state (high or low logic levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components. The
OE inputdoesnotaffecttheinternaloperationoftheflip-flops.Olddatacanbe
retained or new data can be entered while the outputs are in the high-impedance
state.
The ALVCH16823 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16823 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminates the need for pull-up/down resistor.
FUNCTIONAL BLOCK DIAGRAM
2
1OE
1CLR 1
55
1CLKEN
1CLK
1D1
56
54
CE
R
C1
D1
27
2OE
2CLR 28
30
2CLKEN
3 1Q1
2CLK
2D 1
29
42
TO 8 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
CE
R
C1
D1
15
2Q1
TO 8 OTHER CHANNELS
JANUARY 2004
DSC-4237/2

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