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PDF ADIS16100 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16100 | |
| Descripción | Yaw Rate Gyro | |
| Fabricantes | Analog Devices | |
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FEATURES
Complete angular rate gyroscope
Z-axis (yaw rate) response
SPI® digital output interface
High vibration rejection over wide frequency
2000 g powered shock survivability
Externally controlled self test
Internal temperature sensor output
Dual auxiliary 12-bit ADC inputs
Absolute rate output for precision applications
5 V single-supply operation
8.2 mm × 8.2 mm × 5.2 mm package
APPLICATIONS
Platform stabilization
Image stabilization
Guidance and control
Inertial measurement units
±300°/sec Yaw Rate Gyro
with SPI Interface
ADIS16100
GENERAL DESCRIPTION
The ADIS16100 is a complete angular rate sensor (gyroscope)
that uses the Analog Devices surface-micromachining process
to make a functionally complete angular rate sensor with an
integrated serial peripheral interface (SPI).
The digital data available at the SPI port is proportional to the
angular rate about the axis normal to the top surface of the
package (see Figure 19). A single external resistor can be used to
increase the measurement range. An external capacitor can be
used to lower the bandwidth.
Access to an internal temperature sensor measurement is
provided, through the SPI, for compensation techniques.
Two pins are available to the user to input analog signals for
digitization. An additional output pin provides a precision
voltage reference. Two digital self-test inputs electro-
mechanically excite the sensor to test operation of the
sensor and the signal conditioning circuits.
The ADIS16100 is available in an 8.2 mm × 8.2 mm × 5.2 mm,
16-terminal, peripheral land grid array (LGA) package.
FUNCTIONAL BLOCK DIAGRAM
FILT
COUT
RATE
ADIS16100
±300°/s
GYROSCOPE
TEMP
SENSOR
MUX/ADC
4-CHANNE L
SPI
VREF
REF
COM
ST1 ST2
VCC
VDRIVE
+5V +3V TO +5V
Figure 1.
SCLK
DIN
CS
DOUT
AIN2
AIN1
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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ADIS16100
TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 3.
Parameter
fSCLK 2
tCONVERT
tQUIET
t2
t3 3
t43
t5
t6
t7
t8 4
t9
t10
t11
t12
VCC = VDR = 5
10
20
16 × tSCLK
50
10
30
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
μs max
Description
Minimum quiet time required between CS rising edge and start of next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full power-down/auto shutdown modes
1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans
from 4.75 V to 5.25 V.
2 Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 V × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 5 of 16
5 Page 
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THEORY OF OPERATION
The ADIS16100 operates on the principle of a resonator gyro.
Two polysilicon sensing structures each contain a dither frame,
which is electrostatically driven to resonance. This produces the
necessary velocity element to produce a Coriolis force during
angular rate. At two of the outer extremes of each frame, orthogo-
nal to the dither motion, are movable fingers that are placed
between fixed pickoff fingers to form a capacitive pickoff structure
that senses Coriolis motion. The resulting signal is fed to a series
of gain and demodulation stages that produce the electrical rate
signal output. The rate signal is then converted to a digital
representation of the output on the SPI pins. The dual-sensor
design rejects external g-forces and vibration. Fabricating the
sensor with the signal conditioning electronics preserves signal
integrity in noisy environments.
The electrostatic resonator requires 14 V to 16 V for operation.
Because only 5 V is typically available in most applications, a
charge pump is included on-chip.
After the demodulation stage, there is a single-pole, low-pass
filter included on-chip that is used to limit high frequency
artifacts before final amplification. A second single-pole, low-
pass filter is set up via the bandwidth limit capacitor, COUT. This
pole acts as the primary filter within the system (see the Increasing
Measurement Range section).
SUPPLY AND COMMON CONSIDERATIONS
Power supply noise and transient behaviors can influence the
accuracy and stability of any sensor-based measurement system.
When considering the power supply for the ADIS16100, it is
important to understand that the ADIS16100 provides 0.2 μF of
decoupling capacitance on the VCC pin. Depending on the level
of noise present in the system power supply, the ADIS16100
may not require any additional decoupling capacitance for this
supply. The analog supply, VCC, and the digital drive supply,
VDRIVE, are segmented to allow multiple logic levels to be used in
receiving the digital output data. VDRIVE is intended for the
down-stream logic power supply and supports standard 3.3 V
and 5 V logic families. The VDRIVE supply does not have internal
decoupling capacitors.
INCREASING MEASUREMENT RANGE
The full-scale measurement range of the ADIS16100 is increased
by placing an external resistor between the RATE pin and the
FILT pin. This external resistor would be in parallel with an
internal 180 kΩ, 1% resistor. For example, a 330 kΩ external
resistor gives ~50% increase in the full-scale range. This is
effective for up to a 4× increase in the full-scale range
(minimum value of the parallel resistor allowed is 45 kΩ). The
internal circuitry headroom requirements prevent further
increase in the linear full-scale output range.
ADIS16100
The trade-off associated with increasing the full-scale range are
potential increase in output null drift (as much as 2°/sec over
temperature) and introducing initial null bias errors that must
be calibrated.
SETTING BANDWIDTH
The ADIS16100 provides the ability to reduce the bandwidth.
This important feature enables a simple method for achieving
optimal bandwidth/noise trade-offs. An external capacitor can
be used in combination with an on-chip resistor to create a low-
pass filter to limit the bandwidth of the ADIS16100’s rate response.
The −3 dB frequency is defined as
( ( ))fOUT = 1/ 2× π × ROUT × COUT + 0.022 μF
where ROUT represents an internal impedance that was trimmed
during manufacturing to 180 kΩ ± 1%.
Any external resistor applied between the RATE pin and the
FILT pin results in
( ) ( )ROUT = 180 kΩ × REXT / 180 kΩ + REXT
With COUT = 0 μF, a default −3 dB frequency response of 40 Hz
is obtained, based upon an internal 0.022 μF capacitor imple-
mented on-chip.
SELF-TEST FUNCTION
The ADIS16100 includes a self-test feature that actuates each of
the sensing structures and associated electronics in the same
manner, as if subjected to angular rate. It provides a simple
method for exercising the mechanical structure of the sensor,
along with the entire signal processing circuit. It is activated by
standard logic high levels applied to Input ST1, Input ST2, or
both. ST1 causes a change in the digital output equivalent to
typically −221 LSB, and ST2 causes an opposite +221 LSB
change. The self-test response follows the viscosity temperature
dependence of the package atmosphere, approximately
0.25%/°C.
Activating both ST1 and ST2 simultaneously is not damaging.
Because ST1 and ST2 are not necessarily closely matched,
actuating both simultaneously can result in an apparent null
bias shift.
CONTINUOUS SELF TEST
As an additional failure detection measure, power-on self test
can be performed. However, some applications warrant a
continuous self test-while-sensing rate.
Rev. A | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADIS16100.PDF ] | |
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