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PDF ADG3123 Data sheet ( Hoja de datos )
| Número de pieza | ADG3123 | |
| Descripción | 8-Channel CMOS Logic to High Voltage Level Translator | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
2.3 V to 5.5 V input voltage range
Output voltage levels (VDDA and VDDB to VSS ≤ 35 V)
Low output voltage levels: down to −24.2 V
High output voltage levels: up to +35 V
Rise/fall time: 12 ns/19.5 ns typical
Propagation delay: 80 ns typical
Operating frequency: 100 kHz typical
Ultralow quiescent current: 65 μA typical
20-lead, Pb-free, TSSOP package
APPLICATIONS
Low voltage to high voltage translation
TFT-LCD panels
Piezoelectric motor drivers
GENERAL DESCRIPTION
The ADG3123 is an 8-channel, noninverting CMOS to high
voltage level translator. Fabricated on an enhanced LC2MOS
process, the device is capable of operating at high supply
voltages while maintaining ultralow power consumption.
The internal architecture of the device ensures compatibility with
logic circuits running from supply voltages within the 2.3 V to
5.5 V range. The voltages applied to Pin VDDA, Pin VDDB, and
Pin VSS set the logic levels available at the outputs on the Y side
of the device. Pin VDDA and Pin VDDB set the high output level
for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The
VSS pin sets the low output level for all channels. The ADG3123
can provide output voltages levels down to −24.2 V for a low input
level and up to +35 V for a high input logic level. For proper
operation, VDDB must always be greater than or equal to VDDA
and the voltage between the Pin VDDB and Pin VSS should not
exceed 35 V.
The low output impedance of the channels guarantees fast rise
and fall times even for significant capacitive loads. This feature,
combined with low propagation delay and low power consumption,
makes the ADG3123 an ideal driver for TFT-LCD panel
applications.
8-Channel CMOS Logic to
High Voltage Level Translator
ADG3123
FUNCTIONAL BLOCK DIAGRAM
VDDA
A1
A2
A3
A4
A5
A6
GND
ADG3123
6
CHANNELS
Y1
Y2
Y3
Y4
Y5
Y6
VSS
A7
2
A8 CHANNELS
Y7
Y8
VDDB
Figure 1.
The ADG3123 is guaranteed to operate over the −40°C to +85°C
temperature range and is available in a compact, 20-lead TSSOP,
Pb-free package.
PRODUCT HIGHLIGHTS
1. Compatible with a wide range of CMOS logic levels.
2. High output voltage levels.
3. Fast rise and fall times coupled with low propagation delay.
4. Ultralow power consumption.
5. Compact, 20-lead TSSOP, RoHS-compliant package.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADG3123
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VDDA/VDDB to VSS
VDDB to GND
VDDA to GND
VSS to GND
Digital Inputs1
Load Current Per Device
Average
Peak Current2
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
Reflow Soldering (Pb-Free)
Peak Temperature
Time at Peak Temperature
Rating
44 V
−0.3 V to +32 V
−0.3 V to VDDB
+0.3 V to −32 V
VSS − 0.3 V to VDDB + 0.3 V or
20 mA, whichever occurs first
15 mA at 25°C
8 mA at 85°C
150 mA at 25°C
80 mA at 85°C
−40°C to +85°C
−65°C to +125°C
150°C
78°C/W3
260 (+0/−5)°C
10 seconds to 40 seconds
1 Overvoltage at Pin A1 to Pin A8 is clamped by internal diodes. Limit the
current to the maximum ratings given.
2 Pulsed at 100 kHz; 10% duty cycle maximum with the load shown in Figure 2.
3 Guaranteed when the device is soldered on a 4-layer board.
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
Rev. B | Page 4 of 12
5 Page 
ADG3123
THEORY OF OPERATION
The ADG3123 is an 8-channel, noninverting CMOS to high
voltage level translator. Fabricated on an enhanced LC2MOS
process, the device is capable of operating at high supply
voltages while maintaining ultralow power consumption.
The device requires a dual-supply voltage, VDDB and VSS, which
sets the low logic levels for all outputs and the high logic levels
for the Y7 and Y8 outputs. The VDDA pin acts as an analog input.
The voltage applied to the VDDA pin sets the output high logic
level for the Y1 to Y6 outputs.
The device translates the CMOS logic levels applied to the A1 to
A8 inputs into high voltage bipolar levels available on the Y side
of the device at Pin Y1 to Pin Y8.
To ensure proper operation, VDDB must always be greater than
or equal to VDDA and the voltage between the Pin VDDB and
Pin VSS should not exceed 35 V.
INPUT DRIVING REQUIREMENTS
The ADG3123 design ensures low input capacitance and leakage
current thereby reducing the loading of the circuit that drives the
input pins (Pin A1 to Pin A8) to a minimum. Its input threshold
levels are compliant with JEDEC standards for drivers operated
from supply voltages between 2.3 V and 5.5 V. It is recommended
that the inputs of any unused channel be tied to a stable logic
level (low or high).
OUTPUT LOAD REQUIREMENTS
The low output impedance of the ADG3123 allows each channel
to drive both resistive and capacitive loads. The maximum load
current is limited by the current carrying capability of any given
channel. If more channels are used, the maximum load current
per channel is reduced accordingly. Note that the sum of the
load currents on all channels should never exceed the absolute
maximum ratings specifications.
The average load current on each channel, ICHANNEL, can be
determined using the formulas shown in the Capacitive Loads
and the Resistive Loads sections.
Data Sheet
Capacitive Loads
ICHANNEL (A) = FO × CL × (VDDX + |VSS|)
where:
FO is the frequency of the signal applied to the channel in Hz.
CL is the load capacitance in farads.
VSS is the voltage applied to the VSS pin.
VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs.
Resistive Loads
ICHANNEL (A)
=
D ×VDDX
+ (1 − D)×
RL
VSS
where:
D is the duty cycle of the input signal. D is defined as the ratio
between the high state duration of the signal and its period.
RL is the load resistor in Ω.
VSS is the voltage applied to the VSS pin.
VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs.
POWER SUPPLIES
The ADG3123 operates from a dual-supply voltage. As good
design practice for all CMOS devices dictates, power up the
ADG3123 first (VDDB and VSS) before applying the signals to its
inputs (A1 to A8 and VDDA). To ensure correct operation of the
ADG3123, the voltage applied to the VDDB pin must always be
greater than or equal to VDDA and the voltage between the
Pin VDDB and Pin VSS should not exceed 35 V.
To ensure optimum performance, use decoupling capacitors on
all power supply pins. Furthermore, good engineering and layout
practice suggests placing these capacitors as close as possible to
the package supply pins.
Rev. B | Page 10 of 12
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADG3123.PDF ] | |
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