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PDF AD8368 Data sheet ( Hoja de datos )

Número de pieza AD8368
Descripción Linear-in-dB VGA
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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FEATURES
Analog variable gain range: −12 dB to +22 dB
Linear-in-dB scaling: 37.5 dB/V
3 dB bandwidth: 800 MHz @ VGAIN = 0.5 V
Integrated rms detector
P1dB: 16 dBm @ 140 MHz
Output IP3: 33 dBm @ 140 MHz
Noise figure at maximum gain: 9.5 dB @ 140 MHz
Input and output impedances: 50 Ω
Single-supply voltage from 4.5 V to 5.5 V
RoHS-compliant, 24-lead LFCSP
APPLICATIONS
Complete IF AGC amplifiers
Gain trimming and leveling
Cellular base stations
Point-to-point radio links
RF instrumentation
GENERAL DESCRIPTION
The AD8368 is a variable gain amplifier (VGA) with analog
linear-in-dB gain control that can be used from low frequencies
to 800 MHz. Its excellent gain range, conformance, and flatness
are attributed to the Analog Devices, Inc., X-AMP® architecture,
an innovative technique for implementing high performance
variable gain control.
The gain range of −12 dB to +22 dB is scaled accurately to
37.5 dB/V with excellent conformance error. The AD8368 has
a 3 dB bandwidth of 800 MHz that is nominally independent
of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum
gain. The output noise floor is −143 dBm/Hz, which corresponds
to a 9.5 dB noise figure at maximum gain. The single-ended
input and output impedances are nominally 50 Ω.
The gain of the AD8368 can be configured to be an increasing
or decreasing function of the gain control voltage depending
on whether the MODE pin is pulled to the positive supply or
to ground, respectively. When MODE is pulled high, the
AD8368 operates as a typical VGA with increasing gain.
800 MHz, Linear-in-dB
VGA with AGC Detector
AD8368
ICOM 16
OCOM 6
GAIN 1
OCOM 7
INPT 19
ICOM 17
ICOM 18
ICOM 20
FUNCTIONAL BLOCK DIAGRAM
VPSO
MODE VPSO VPSI VPSI VPSI VPSI VPSI
10 21 9 11 12 22 23 13
AD8368
GAIN INTERPOLATOR
FIXED-GAIN
AMPLIFIER
OUTPUT
BUFFER
24 ENBL
gm STAGES
0dB –2dB –4dB
–36dB
50
DECL
ATTENUATOR LADDER
REF
X2
+
8 OUTP
3 HPFL
4 DECL
14 DECL
15 DECL
Figure 1.
2
DETO
5
DETI
By connecting MODE to ground and using the on-board rms
detector, the AD8368 can be configured as a complete
automatic gain control (AGC) system with RSSI. The output
power is accurately leveled to the internal default setpoint of
63 mV rms (−11 dBm referenced to 50 Ω), independent of the
waveform crest factor. Because the uncommitted detector
input is available at DETI, the AGC loop can level the signal at
the AD8368 output or at any other point in the signal chain
over a maximum input power range of 34 dB. Furthermore, the
setpoint level can be raised by dividing down the output signal
before applying it to the detector.
The AD8368 operates from a supply voltage of 4.5 V to 5.5 V
and consumes 60 mA of current. It can be fully powered down
to <3 mA by grounding the ENBL pin. The AD8368 is fabricated
using the Analog Devices proprietary SiGe SOI complementary
bipolar IC process. It is available in a 24-lead LFCSP and
operates over the industrial temperature range of −40°C to
+85°C. Application boards are available upon request.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved.

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AD8368 pdf
AD8368
VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted.
Table 2.
Parameter
SQUARE LAW DETECTOR (DETI, DETO)
Output Setpoint
DETI DC Bias Level to ICOM
DETI Impedance
DETO Output Range1
AGC Step Response
MODE CONTROL INTERFACE (MODE)
MODE Threshold
MODE Input Bias Current
POWER INTERFACE (VPSI, VPSO)
Supply Voltage
Total Supply Current
Disable Current
ENABLE INTERFACE (ENBL)
Enable Threshold
Enable Response Time
ENBL Input Bias Current
Min Typ Max Unit Conditions
−11 dBm OUTP connected to DETI
VS/2 V
710 Ω
0.6 pF
0.1 VS/2 V
30 μs For −6 dB input power step (CDETO = 1 nF)
3.5
50
V
μA
4.5 5
5.5 V
60 mA ENBL high
2 mA ENBL low
2.5 V
1.5 μs
3 μs
150 μA
Time delay following off-to-on transition until output
reaches 90% of final value
Time delay following on-to-off transition until supply
current is less than 5 mA
VENBL = 5 V
1 Refer to AGC Operation section.
Rev. B | Page 4 of 20

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AD8368 arduino
AD8368
1.0 1.0
0.9 0.8
0.8 0.6
0.7 0.4
0.6 0.2
0.5
0.4
0.3
+25°C
0.2
+85°C
+25°C
–40°C
0
–0.2
–0.4
–0.6
0.1
–40°C
0
–40 –35
+85°C
–30 –25 –20 –15 –10
RF INPUT (dBm)
–5
0
–0.8
–1.0
5
Figure 21. RSSI (VDETO) and Conformance Error vs. Input Power (f = 70 MHz)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
–40°C
0.2
+85°C
+25°C
–40°C
0.1
+25°C
0
–40 –35
+85°C
–30
–25 –20 –15 –10
RF INPUT (dBm)
–5
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
5
Figure 22. RSSI (VDETO) and Conformance Error vs. Input Power (f = 140 MHz)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
–40°C
0.2
+85°C
+25°C
–40°C
0.1
+25°C
0
–40 –35
+85°C
–30
–25 –20 –15 –10
RF INPUT (dBm)
–5
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
5
Figure 23. RSSI (VDETO) and Conformance Error vs. Input Power (f = 240 MHz)
1.0 1.0
0.9 0.8
0.8 0.6
0.7
+85°C
0.4
0.6 0.2
0.5
0.4
0.3
–40°C
0.2
–40°C
+25°C
0
–0.2
–0.4
–0.6
0.1
+25°C
0
–40 –35
+85°C
–30 –25 –20 –15 –10
RF INPUT (dBm)
–5
0
–0.8
–1.0
5
Figure 24. RSSI (VDETO) and Conformance Error vs. Input Power (f = 380 MHz)
VRSSI
VOUTP
CH2 50mV CH3 100mV M20µs 500MS/s A CH1 410mV
2.0ns/PT
Figure 25. AGC Time Domain Response (3 dB Power Step, CDETO = 1 nF)
80
70
60 4.5V
50
40 5.0V
30
20
10
0
–40 –20
5.5V
5.5V
5.0V
4.5V
0 20 40
TEMPERATURE (°C)
60
8
7
6
5
4
3
2
1
0
80
Figure 26. Supply Current and Disable Current vs. Temperature
Rev. B | Page 10 of 20

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