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PDF ICS91857 Data sheet ( Hoja de datos )
| Número de pieza | ICS91857 | |
| Descripción | Value SSTL_2 Clock Driver | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS91857
Value SSTL_2 Clock Driver (60MHz - 220MHz)
Recommended Application:
Zero delay board fan-out memory modules
Product Description/Features:
• Meets PC3200 specification for DDRI-400 support
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
Switching Characteristics:
• CYCLE - CYCLE jitter (>100MHz):<75ps
• OUTPUT - OUTPUT skew: <100ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PD#
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUTC
32 FB_OUTT
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Functionality
Block Diagram
INPUTS
AVDD PD# CLK_INT
OUTPUTS
CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
L
H
H
X
HL
LH
HL
LH
HL
<20MHz)(1)
HL
ZZ
ZZ
LH
HL
ZZ
H
Z
Z
L
H
Z
L Bypassed/off
Z off
Z off
H on
L on
Z off
PD#
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
0494C—08/15/05
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
1 page  
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ICS91857
Recommended Operating Condition for DDR200/266/333 (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Supply Voltage
Low level input voltage
VDDQ, AVDD
VIL
CLKT, CLKC, FB_INC
PD#
2.3
-0.3
High level input voltage
CLKT, CLKC, FB_INC
VIH PD#
VDDQ/2 + 0.18
1.7
DC input signal voltage
(note 2)
-0.3
Differential input signal
voltage (note 3)
DC - CLKT, FB_INT
VID AC - CLKT, FB_INT
0.36
0.7
Output differential cross-
voltage (note 4)
VOX
VDDQ/2 - 0.15
Input differential cross-
voltage (note 4)
VIX
VDDQ/2 - 0.2
High level output
current
IOH
MAX UNITS
2.7 V
VDDQ/2 - 0.18
0.7
V
V
V
VDDQ + 0.6
V
VDDQ
V
VDDQ + 0.6
VDDQ + 0.6
V
V
VDDQ/2 + 0.15 V
VDDQ/2 + 0.2 V
0.12 mA
Low level output current
IOL
12 mA
Input slew rate
Operating free-air
temperature
SR
TA
1
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
4 V/ns
70 °C
0494C—08/15/05
5
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ICS91857
YX, FB_OUTC
YX, FB_OUTT
Parameter Measurement Information
t(hper_n)
t(hper_n+1)
1
fo
t(jit_Hper) = t(jit_Hper_n) - 1
2xfO
Figure 7. Half-Period Jitter
80%
Clock Inputs
and Outputs
20%
tslrr(i)
tslrf(i) slrf(o)
80%
VID, VOD
20%
Figure 8. Input and Output Slew Rates
0494C—08/15/05
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS91857.PDF ] | |
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