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PDF NCP1308 Data sheet ( Hoja de datos )
| Número de pieza | NCP1308 | |
| Descripción | PWM Current Mode Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP1308
PWM Current−Mode
Controller for Free−Running
Quasi−Resonant Operation
The NCP1308 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/Critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 10 ms
timer prevents the free−run frequency to exceed a high frequency
(therefore below the 150 kHz CISPR−22 EMI starting limit), while
the skip adjustment capability lets the user select the frequency at
which the burst foldback takes place.
The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1308. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Thanks to its high−voltage technology, the IC is
directly connected to the high−voltage DC rail. As a result, the
short−circuit trip point is not dependent upon any VCC auxiliary
level.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin. If an OVP is detected on
the VCC pin, the IC permanently latches off.
Finally, the continuous feedback signal monitoring implemented
with an Overcurrent fault Protection circuitry (OCP) makes the final
design rugged and reliable.
Features
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
• Current−Mode with Adjustable Skip Cycle Capability
• Dynamic Self−Supply Type of VCC
• Auto−Recovery Overcurrent Protection
• Improved UVLO for VCC below 10 V
• Latching Overvoltage Protection on VCC
• 500 mA Peak Current Source/Sink Capability
• Internal 1.0 ms Soft−Start
• Internal 10 ms Minimum TOFF
• Adjustable Skip Level
• Internal Temperature Shutdown
• Internal Leading Edge Blanking
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
• This is a Pb−Free Device
Typical Applications
• AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
http://onsemi.com
8
1
SOIC−8
DR SUFFIX
CASE 751
MARKING
DIAGRAM
8
1308
ALYW
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
Dmg 1
FB 2
CS 3
GND 4
8 HV
7
6 VCC
5 Drv
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1308DR2G SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 2
DataSheet4 U .com
1
Publication Order Number:
NCP1308/D
1 page  
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NCP1308
TYPICAL CHARACTERISTICS
120 1.20
100 1.15
80 1.10
60 1.05
40 1.00
20 0.95
0
−25 0
0.90
25 50 75 100 125
−25 0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. Demagnetization Threshold
vs. Temperature
Figure 4. Maximum Peak Current Setpoint
vs. Temperature
18 1.60
18 1.40
17 1.20
17 1.00
16 0.80
16 0.60
15
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 5. OVP Level Threshold vs. Temperature
0.40
−25
0 25 50 75 100
TEMPERATURE (°C)
Figure 6. Internal IC Consumption
(No Output Load) vs. Temperature
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 7. Internal IC Consumption (1.0 nF Load)
vs. Temperature
125
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NCP1308
Shutting off the NCP1308
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 21. When
OFF, Q1 is transparent to the operation. When forward
biased, the transistor pulls the FB pin to ground (VCEsat ≈
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering
ON/OFF
10 k
Q1
10 nF
NCP1308
18
27
36
45
Figure 21. A Simple Bipolar Transistor Totally
Disables the IC
Power Dissipation
The SOIC package offers a 178°C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decreasing this number: 12 mm x 12 mm to drop
RθJA down to 100°C/W with 35 mm copper thickness (1 oz)
or 6.5 mm x 6.5 mm with 70 mm copper thickness (2 oz).
As one can see, the designer must be cautious when using
the SO−8 package to check if its thermal performance is
compatible with the total power dissipation. The power
dissipation is simply Vbulk (high line) x IDSS,AVG. The
IDSS,AVG parameter can be measured by inserting an
amp−meter in series with the HV pin and compute its
average value.
We therefore recommend the insertion of a resistor from
the bulk connection to the HV pin. This will help to:
1. Avoid negative spikes at turn−off on the HV pin
(see below)
2. Split the power budget between this resistor and
the package. The resistor is calculated by leaving
at least 50 V on pin 8 at minimum input voltage
(suppose 100 Vdc in our case):
Rdrop
v
Vbulkmin *
7.0 mA
50
V
t
7.1
kW
.
The power dissipated by the resistor is thus:
Pdrop
+
VdropRMS2
Rdrop
(IDSS @ Rdrop @ Ǹ DSSduty−cycle)2
+ Rdrop
(7.0 mA @ 7.1 kW @ Ǹ0.286) 2
+ 7.1 kW
+ 99.5 mW
where IDSS is the peak DSS capability, DSSduty−cycle is the
duty−cycle of the DSS, that is to say, the time it is on and
the time it stays off (DSSduty−cycle = on/(on + off) ).
Please refer to the application note AND8069/D
available at www.onsemi.com/pub/ncp1200.
If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary winding
and the VCC pin which will disable the DSS operation
(VCC > 10 V).
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short−circuit protection.
A short−circuit actually forces the output voltage to be at
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please
note that this can also happen in case of feedback loss, e.g.
a broken optocoupler. To account for this situation,
NCP1308 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low duty−cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends
on normal output load conditions and the maximum peak
current allowed by the system. The timeout used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the VCCOFF level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents
the self−supply current source to restart and puts all the
circuitry in standby, consuming as little as 330 mA typical
(ICC3 parameter). As a result, the VCC level slowly
discharges toward 0. When this level crosses 5.3 V typical,
the controller enters a new startup phase by turning the
current source on: VCC rises toward 12 V and again delivers
output pulses at the VCCOFF crossing point. If the fault
condition has been removed before VCCON approaches,
then the IC continues its normal operation. Otherwise, a
new fault cycle takes place. Figure 22 on the following
page shows the evolution of the signals in presence of a
fault.
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet NCP1308.PDF ] | |
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