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PDF ADN2530 Data sheet ( Hoja de datos )
| Número de pieza | ADN2530 | |
| Descripción | 11.3 Gbps Active Back-Termination | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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11.3 Gbps, Active Back-Termination,
Differential VCSEL Driver
ADN2530
FEATURES
Up to 11.3 Gbps operation
−40°C to +100°C operation
Very low power: ISUPPLY = 65 mA
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor
APPLICATIONS
10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers
GENERAL DESCRIPTION
The ADN2530 laser diode driver is designed for direct modula-
tion of packaged VCSELs with a differential resistance ranging
from 35 Ω to 140 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from −40°C to +100°C.
DATAP
DATAN
FUNCTIONAL BLOCK DIAGRAM
VCC
CPA
ALS
VCC
VCC ADN2530
50Ω 50Ω
GND
CROSS
POINT
ADJUST
100Ω
IMOD
VCC
800Ω
800Ω
IMODP
IMODN
IBMON
IBIAS
200Ω
200Ω 200Ω
10Ω
MSET
GND
BSET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage—VCC to GND
IMODP, IMODN to GND
DATAP, DATAN to GND
All Other Pins
Junction Temperature
Storage Temperature Range
Soldering Temperature
(Less than 10 sec)
Rating
−0.3 V to +4.2 V
VCC − 1.5 V to +4.5 V
VCC − 1.8 V to VCC − 0.4 V
−0.3 V to VCC + 0.3 V
150°C
−65°C to +150°C
300°C
ADN2530
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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Rev. A | Page 5 of 20
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The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 25 to Figure 27.
VCC
BSET
800Ω
VCC
200Ω
Figure 25. Equivalent Circuit of the BSET Pin
IBIAS
VCC
VCC
2kΩ
100Ω
10Ω
Figure 26. Equivalent Circuit of the IBIAS Pin
VCC
VCC
500Ω
VCC
100Ω
IBMON
Figure 27. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 28.
TO LASER CATHODE
VBSET
IBIAS
ADN2530
BSET IBMON
GND
L IBIAS
RIBMON
750Ω
ADN2530
See the Headroom Calculations section for examples.
The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see Table 6.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5.
Table 5.
ALS Logic State
High
Low
Floating
IBIAS and IMOD
Disabled
Enabled
Enabled
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 29.
VCC
VCC
ALS
100Ω
35kΩ
2kΩ
Figure 29. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 30.
VCC
FROM CPA STAGE
MSET
800Ω
100Ω IMOD
IMODP
IMODN
Figure 28. Recommended Configuration for BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (2 mA and 25 mA), but it can be calculated for
any bias current by
VCOMPLIANCE (V) = VCC (V) − 0.75 − 22 × IBIAS (A)
200Ω
GND
ADN2530
Figure 30. Generation of Modulation Current on the ADN2530
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.
Rev. A | Page 11 of 20
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| PDF Descargar | [ Datasheet ADN2530.PDF ] | |
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