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PDF ADN2525 Data sheet ( Hoja de datos )
| Número de pieza | ADN2525 | |
| Descripción | 10.7 Gbps Active Back-Termination | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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10.7 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2525
FEATURES
Up to 10.7 Gbps operation
Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA)
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
PECL-/CML-compatible data inputs
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP package
Voltage input control for bias and modulation currents
XFP-compliant bias current monitor
Optical evaluation board available
APPLICATIONS
SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/XPAK/MSA 300 optical modules
SR and VSR optical links
GENERAL DESCRIPTION
The ADN2525 laser diode driver is designed for direct modula-
tion of packaged laser diodes having a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2525 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly mis-
terminated. The small package provides the optimum solution
for compact modules where laser diodes are packaged in low
pin-count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The automatic
laser shutdown feature allows the user to turn on/off the bias
and modulation currents by driving the ALS pin with the
proper logic levels.
The product is available in a space-saving 3 mm × 3 mm LFCSP
package specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VCC
ALS
VCC
VCC
ADN2525
DATAP
DATAN
50Ω 50Ω
GND
IMOD 50Ω
VCC
IMODP
IMODN
800Ω
800Ω
IBMON
IBIAS
200Ω
200Ω
200Ω 2Ω
MSET
GND
BSET
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VCC to GND
IMODP, IMODN to GND
DATAP, DATAN to GND
All Other Pins
Junction Temperature
Storage Temperature
Soldering Temperature
(Less than 10 sec)
Min
−0.3
VCC − 1 .5
VCC − 1.8
−0.3
−65
Max
+4.2
4.75
VCC − 0.4
VCC + 0.3
150
+150
240
Unit
V
V
V
V
°C
°C
°C
ADN2525
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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Rev. 0 | Page 5 of 16
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This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination. The
equivalent circuits for MSET, IMODP, and IMODN are shown
in Figure 26 and Figure 27.
VCC
VCC
MSET
800Ω
200Ω
Figure 26. Equivalent Circuit of the MSET Pin
VCC IMODN
25Ω
IMODP VCC
25Ω
3.3Ω 3.3Ω
Figure 27. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 28. See Table 5 for recom-
mended components.
VMSET
IBIAS
VCC
ADN2525
IMODP
LL
Z0 = 25Ω C Z0 = 25Ω
MSET IMODN
GND
TOSA
Z0 = 25Ω C Z0 = 25Ω
LL
VCC VCC
Figure 28. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
ADN2525
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value as shown
in Figure 29.
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
0
MAXIMUM
TYPICAL
MINIMUM
5 10 15 20 25 30 35 40 45 50 55
DIFFERENTIAL LOAD RESISTANCE
Figure 29. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2525 (IMODP, IMODN pins) must be
ac-coupled to the load. The voltages at these pins have a dc
component equal to VCC, and an ac component with single-
ended peak-to-peak amplitude of IMOD × 25 Ω. This is the
case even if the load impedance is less than 50 Ω differential,
since the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for this pin over supply,
temperature, and modulation current range as shown in
Figure 30. See the Applications Information section for
example headroom calculations.
VIMODP, IMODN
VCC + 1.1V
VCC
VCC – 1.1V
NORMAL OPERATION REGION
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Rev. 0 | Page 11 of 16
Figure 30. Allowable Range for the Voltage at
IMODP and IMODN
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADN2525.PDF ] | |
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