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PDF ADP3168 Data sheet ( Hoja de datos )
| Número de pieza | ADP3168 | |
| Descripción | 4-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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6-Bit, Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3168
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current balancing between all output phases
Built-in Power Good/crowbar blanking supports
On-the-fly VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for:
Next generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3168 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation, allowing for the construc-
tion of up to four complementary buck switching stages.
The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3168 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed Power Good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The device is specified over the commercial temperature range
of 0°C to 85°C and is available in a 28-lead TSSOP package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14 13
ADP3168
11
EN
UVLO
SHUTDOWN
AND BIAS
19
GND DAC
+150mV
CSREF
DAC
–250mV
10
PWRGD
DELAY
15
ILIMIT
EN
12
DELAY
SOFT-
START
OSCILLATOR
CMP
SET EN
RESET
27
PWM1
CURRENT-
BALANCING
CIRCUIT
CMP RESET
26
2-, 3-, 4-PHASE PWM2
DRIVER LOGIC
CMP RESET
25
PWM3
CMP RESET
CROWBAR
CURRENT
LIMIT
CURRENT-
LIMIT
CIRCUIT
24
PWM4
23
SW1
22
SW2
21
SW3
20
SW4
17
CSSUM
16
CSREF
18
CSCOMP
9
COMP
8
FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
12 3456
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
VID0 to VID5, EN, DELAY, ILIMIT,
CSCOMP, RT, PWM1 to PWM4, COMP
SW1-SW4
All Other Inputs and Outputs
Operating Ambient Temperature
Range
Operating Junction Temperature
Storage Temperature Range
Junction to Air Thermal Resistance (θJA)
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +15 V
−0.3 V to +0.3 V
−0.3 V to +5.5 V
−5 V to +25 V
−0.3 V to VCC + 0.3 V
0°C to 85°C
125°C
−65°C to +150°C
100°C/W
300°C
215°C
220°C
ADP3168
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
DataSheet4 U .com
Rev. B | Page 5 of 24
5 Page 
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ADP3168
The latch-off function can be reset either by removing and
reapplying VCC to the ADP3168, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.
Figure 8. Start-Up Waveforms, Circuit of Figure 12. Channel 1—PWRGD,
Channel 2—VOUT, Channel 3—High-Side MOSFET VGS,
Channel 4—Low-Side MOSFET VGS
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3168 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current-limit threshold of
10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current-limit latch-off delay time is
therefore set by the RC time constant discharging from 3 V to
1.8 V. The Application Information section discusses the
selection of CDLY and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft-start cycle is initiated.
Figure 9. Overcurrent Latch-Off Waveforms, Circuit of Figure 11. Channel 1—
PWRGD, Channel 2—VOUT, Channel 3—CSCOMP Pin of ADP3168,
Channel 4—High-Side MOSFET VGS
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current-balance
circuitry.
There is also an inherent per-phase current limit that protects
individual phases in the case where one or more phases stop
functioning because of a faulty component. This limit is based
on the maximum normal mode COMP voltage.
DataSheet4 U .com
Rev. B | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP3168.PDF ] | |
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