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PDF T14L1024N Data sheet ( Hoja de datos )
| Número de pieza | T14L1024N | |
| Descripción | 128K X 8 HIGH SPEED CMOS STATIC RAM | |
| Fabricantes | Taiwan Memory Technology | |
| Logotipo |  |
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tm TE
CH
SRAM
T14L1024N
128K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
• Fast Address Access Times : 10/12/15ns
• Single 3.3V ±0.3V power supply
• Center power/ground pin configuration
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
- 32-pin 300 mil and 400 mil SOJ
- 32-pin TSOP 8x13.4mm and 8x20mm
- 36-Ball CSP (8x10mm)
PART NUMBER EXAMPLES
PACKAGE
SPEED
T14L1024N-10J SOJ 300mil
10ns
T14L1024N-10W SOJ 400 mil
10ns
T14L1024N-10P TSOP 8x13.4mm 10ns
T14L1024N-10H TSOP 8x20mm 10ns
T14L1024N-10C 36-Ball CSP
10ns
GENERAL DESCRIPTION
The T14L1024N is a one-megabit density, fast
static random access memory organized as
131,072 words by 8 bits. It is designed for
use in high performance memory applications
such as main memory storage and high speed
communication buffers. Fabricated using high
performance CMOS technology, access times
down to 10ns are achieved.
BLOCK DIAGRAM
Vcc
Vss
A0
...
DECODER
.
A16
CORE
ARRAY
CE I/O0
.
DATA I/O ..
WE
OE
I/O7
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O0 - I/O7
CE
WE
OE
Vcc
Vss
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable
Output Enable
Power Supply
Ground
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
DataSheet4 U .com
Publication Date: APR. 2002
Revision: C
1 page  
www.DataSheet4U.com
tm TE
CH
T14L1024N
AC CHARACTERISTICS
(Vcc=3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
SYM. T14L1024N-10
MIN. MAX.
tRC 10 -
tAA - 10
tACS - 10
tAOE
-
6
tCLZ*
3
-
tOLZ*
0
-
tCHZ*
-
5
tOHZ*
-
5
tOH 3 -
T14L1024N-12
MIN. MAX.
12 -
- 12
- 12
-7
3-
0-
-6
-6
3-
T14L1024N-15 UNIT
MIN. MAX.
15 - ns
- 15 ns
- 15 ns
- 7 ns
3 - ns
0 - ns
- 7 ns
- 7 ns
3 - ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
PARAMETER
SYM. T14L1024N-10 T14L1024N-12
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 10 - 12
-
Chip Enable to End of Write
tCW 8
- 10
-
Address Valid to End of Write
tAW 8
- 10
-
Address Setup Time
tAS 0 - 0 -
Write Pulse Width
tWP 8 - 10 -
Write Recovery Time
tWR 0 - 0
-
Data Valid to End of Write
tDW 6 - 8
-
Data Hold from End of Write
tDH 0 - 0
-
Write to Output in High Z
tWHZ*
-
5
-
6
Output Disable to Output in High Z tOHZ*
-
5
-
6
Output Active from End of Write tOW 0 - 0
-
* These parameters are sampled but not 100% tested.
T14L1024N-15 UNIT
MIN. MAX.
15 - ns
11 - ns
11 - ns
0 - ns
11 - ns
0 - ns
8 - ns
0 - ns
- 6 ns
- 7 ns
0 - ns
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
DataSheet4 U .com
Publication Date: APR. 2002
Revision: C
5 Page 
www.DataSheet4U.com
tm TE
CH
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x13.4mm)
T14L1024N
SYMBOL
A
A1
A2
b
C
D
E
HD
e
L
L1
y
θ
Dimension in inches
0.044(MAX)
0.004±0.002
0.041(MAX)
0.008±0.004
0.006±0.001
0.465±0.008
0.315±0.004
0.528±0.008
0.020(TYP.)
0.020±0.004
0.031±0.008
0.002(MAX)
0° ~ 5°
Dimension in mm
1.10(MAX)
0.05±0.05
1.02(MAX)
0.20±0.10
0.15±0.02
11.8±0.2
8.0±0.1
13.4±0.2
0.5(TYP.)
0.5±0.1
0.8±0.2
0.05(MAX)
0° ~ 5°
TM Technology Inc. reserves the right
P. 11
to change products or specifications without notice.
DataSheet4 U .com
Publication Date: APR. 2002
Revision: C
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet T14L1024N.PDF ] | |
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