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PDF AD9380 Data sheet ( Hoja de datos )
| Número de pieza | AD9380 | |
| Descripción | Analog/HDMI Dual-Display Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DataSheet4 U .com
Analog/HDMI
Dual-Display Interface
AD9380
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPrIN0
R/G/B OR YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSDA
DDCSCL
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8 × 3
A/D
OR YCbCr
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
HDMI RECEIVER
R/G/B 8 × 3
OR YCbCr
2 DATACK
DE
HSYNC
VSYNC
4
HDCP
HDCP KEYS
Figure 1.
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2 DATACK
HSOUT
VSOUT
SOGOUT
DE
S/PDIF
8-CHANNEL
I2S
SCLK
MCLK
LRCLK
AD9380
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
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AD9380
Parameter
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
DVDD Supply Voltage
PVDD Supply Voltage
IVD Supply Current (Typical Pattern)1
IVDD Supply Current (Typical Pattern)2
IDVDD Supply Current (Typical Pattern)1, 4
IPVDD Supply Current (Typical Pattern)1
Power-Down Supply Current (IPD)
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew
(TDPS)
Channel to Channel Differential Input
Skew (TCCS)
Low-to-High Transition Time for Data and
Controls (DLHT)
Test
Level
IV
IV
IV
IV
V
V
V
V
VI
IV
IV
IV
Low-to-High Transition Time for
DATACK (DLHT)
IV
IV
High-to-Low Transition Time for Data and
Controls (DHLT)
IV
IV
High-to-Low Transition Time for
DATACK (DHLT)
IV
IV
Clock-to-Data Skew5 (TSKEW)
Duty Cycle, DATACK5
DATACK Frequency (FCIP)
IV
IV
IV
VI
Conditions
AD9380KSTZ-100 AD9380KSTZ-150
Min Typ Max Min Typ Max Unit
3.15 3.3 3.47 3.15 3.3 3.47 V
1.7 3.3 347 1.7 3.3 347 V
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 1.8 1.9 1.7 1.8 1.9 V
80 100
80 110 mA
40 1003
55 1753
88 110
110 145 mA
26 35
30 40 mA
130 130 mA
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
–0.5
45
20
+2.0 −0.5
50
360 ps
6 Clock
Period
900 ps
1300 ps
650 ps
1200 ps
850 ps
1250 ps
800 ps
1200 ps
+2.0 ns
55 %
150 MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
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AD9380
Mnemonic
POWER SUPPLY1
VD (3.3 V)
VDD (1.8 V to 3.3 V)
PVDD (1.8 V)
DVDD (1.8 V)
GND
Description
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins, so output noise transferred into
the sensitive analog circuitry can be minimized. If the AD9380 is interfacing with lower voltage logic, VDD may be
connected to a lower supply voltage (as low as 1.8 V) for compatibility.
Clock Generator Power Supply.
The most sensitive portion of the AD9380 is the clock generation circuitry. These pins provide power to the clock
PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to
these pins.
Digital Input Power Supply.
This supplies power to the digital logic.
Ground.
The ground return for all circuitry on chip. It is recommended that the AD9380 be assembled on a single solid
ground plane, with careful attention to ground current paths.
1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.
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Rev. 0 | Page 11 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9380.PDF ] | |
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