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PDF V6150 Data sheet ( Hoja de datos )
| Número de pieza | V6150 | |
| Descripción | Power Surveillance and Software Monitoring | |
| Fabricantes | ETC | |
| Logotipo |  |
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EM MICROELECTRONIC-MARIN SA
V6150
Power Surveillance and Software Monitoring
Features
n Standby mode, maximum current 45 mA
n Reset output guaranteed for VDD voltage
down to 1.2 V
n Comparator for voltage monitoring,
voltage reference 1.5 V
n Programmable reset voltage monitoring
n Programmable power-on reset (POR) delay
n Watchdog with programmable time window
guarantees a minimum time and a maximum time
between software clearing of the watchdog
n Time base accuracy ± 10%
n System enable (EN) output offers added security
n TTL / CMOS compatible
n -40 to +85 °C temperature range
n On request extended temperature range,
−40 to +125 °C
n DIP8 and SO8 packages
Description
The V6150 offers a high level of integration by voltage
monitoring and software monitoring in an 8 lead
package. A comparator monitors the voltage applied at
the VIN input comparing it with an internal 1.5 V
reference. The power-on reset function is initialized after
VIN reaches 1.5 V and takes the reset output inactive
after TPOR depending of external resistance. The reset
output goes active low when the VIN voltage is less than
1.5 V. The RES and EN outputs are guaranteed to be in
a correct state for a supply voltage as low as 1.2 V. The
watchdog function monitors software cycle time and
execution. If the software clears the watchdog too
quickly (incorrect cycle time) or too slowly (incorrect
execution), it will cause the system to be reset. The
system enable output prevents critical control functions
being activated until software has successfully cleared
the watchdog three times. Such a security could be
used to prevent motor controls being energized on
repeated resets of a faulty system.
Applications
n Automotive systems
n Cellular telephones
n Security systems
n Battery powered products
n Industrial electronics
Typical Operating Configuration
Version 00:
Version 01:
VDD
V6150
R VIN
TCL
VSS
RES
EN
GND
Pin Assignment
DIP8 / SO8
Fig. 1
EN
RES
TCL
VSS
V6150
VIN
R
VDD
NC
Fig. 2
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Block Diagram
V6150
Enable
Logic
EN
Vers.00
Voltage
Reference
VREF - Comparator
Reset
Control
RES
Vers.01
VIN +
R
Current
COosnctirlloaltloedr
Timer
TCL
Open drain
output RES
Fig. 8
Pin Description
Pin Name Function
1 EN
2 RES
3 TCL
4 VSS
5 NC
6 VDD
7R
8 VIN
Vers. 00:
Open drain active low enable output.
EN must be pulled up to VDD even
if unused.
Vers. 01:
Push-pull active low enable output
Open drain active low reset output.
RES must be pulled up to VDD even
if unused
Watchdog timer clear input signal
GND terminal
No connection
Voltage supply
REXT input for RC oscillator tuning
Voltage comparator input
Functional Description
Table 5
VIN Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level on
the VIN input. The external voltage level is typically
obtained from a voltage divider as shown in Fig. 9. The
user defines the external voltage divider to set the
desired threshold level for power-on reset and power-
down reset in his system. The internal comparator
reference voltage is typically 1.52 V.
At power-up the reset output (RES) is held low (see Fig.
5). When VIN becomes greater than VREF, the RES output
is held low for an additional power-on reset (POR) delay
which is equal to the watchdog time TWD (typically 100
ms with an external resistor of 123 kW connected at R
pin). The POR delay prevents repeated toggling of RES
even if VIN and the INPUT voltage drops out and
recovers. The POR delay allows the microprocessor’s
crystal oscillator time to start and stabilize and ensures
correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the power-
down reset whenever VIN falls below VREF. The sensitivity
or reaction time of the internal comparator to the voltage
level on VIN is typically 5 ms.
Timer Programming
The on-chip oscillator with an external resistor REXT
connected between the R pin and VSS (see Fig. 9)
allows the user to adjust the power-on reset (POR)
delay, watchdog time TWD and with this also the closed
and open time windows as well as the watchdog reset
pulse width (TWD/40).
With REXT = 123 kW, the typical delays are:
- Power-on reset delay: TPOR is 100 ms
- Watchdog time:
TWD is 100 ms
- Closed window:
TCW is 80 ms
- Open window:
TOW is 40 ms
- Watchdog reset:
TWDR is 2.5 ms
Note the current consumption increases as the frequen-
cy increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see Fig. 4) and
is defined by two parameters, TWD and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer
resets and is defined by TCW = TWD − OWP(TWD).
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TWD Coefficient versus REXT at TA = +25 °C
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
10
REXT Coefficient versus TWD at TA = +25 °C
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
10
100
REXT [kΩ]
100
TWD [ms]
DataSheet4 U .com
V6150
1000
Fig. 19
1000
Fig. 20
11
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| PDF Descargar | [ Datasheet V6150.PDF ] | |
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