PDF ICS9DB108 Data sheet ( Hoja de datos )

Número de pieza	ICS9DB108
Descripción	Eight Output Differential Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. Eight Output Differential Buffer for PCI-Express ICS9DB108 Recommended Application: DB800 Intel Yellow Cover part with PCI-Express support. Output Features: • 8 - 0.7V current-mode differential output pairs • Supports zero delay buffer mode and fanout mode • Bandwidth programming available Key Specifications: • Outputs cycle-cycle jitter < 50ps • Outputs skew: 50ps • +/- 300ppm frequency accuracy on output clocks Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread • Supports undriven differential output pair in PD# and SRC_STOP# for power management. Pin Configuration SRC_DIV# 1 VDD 2 GND 3 SRC_IN 4 SRC_IN# 5 OE_0 6 OE_3 7 DIF_0 8 DIF_0# 9 GND 10 VDD 11 DIF_1 12 DIF_1# 13 OE_1 14 OE_2 15 DIF_2 16 DIF_2# 17 GND 18 VDD 19 DIF_3 20 DIF_3# 21 BYPASS#/PLL 22 SCLK 23 SDATA 24 48 VDDA 47 GNDA 46 IREF 45 LOCK 44 OE_7 43 OE_4 42 DIF_7 41 DIF_7# 40 GND 39 VDD 38 DIF_6 37 DIF_6# 36 OE_6 35 OE_5 34 DIF_5 33 DIF_5# 32 GND 31 VDD 30 DIF_4 29 DIF_4# 28 HIGH_BW# 27 SRC_STOP# 26 PD# 25 GND 48-pin SSOP & TSSOP 0723D—01/08/04 DataSheet4 U .com 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9DB108 Absolute Max Symbol Parameter VDD_A VDD_In VIL VIH Ts Tambient Tcase ESD prot 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND-0.5 -65 0 2000 Max 4.6 4.6 VDD+0.5V 150 70 115 Units V V V V °C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage Input Low Voltage Input High Current Input Low Current VIH 3.3 V +/-5% 2 VIL 3.3 V +/-5% GND - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 MAX VDD + 0.3 0.8 5 UNITS NOTES V V uA uA uA Operating Supply Current IDD3.3OP Full Active, CL = Full load; 250 mA Powerdown Current IDD3.3PD all diff pairs driven all differential pairs tri-stated 60 mA 12 mA Input Frequency3 Fi VDD = 3.3 V 80 100/133 166/200 220 MHz 3 Pin Inductance1 Lpin 7 nH 1 Input Capacitance1 CIN COUT Logic Inputs Output pin capacitance 1.5 5 pF 1 6 pF 1 PLL Bandwidth when PLL Bandwidth BW PLL_BW=0 PLL Bandwidth when PLL_BW=1 4 MHz 1 2 MHz 1 Clk Stabilization1,2 TSTAB From VDD Power-Up and after input clock stabilization or de- 1 ms 1,2 assertion of PD# to 1st clock Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_SRC_STOP# DIF output enable after SRC_Stop# de-assertion 10 ns 1,3 Tdrive_PD# DIF output enable after PD# de-assertion 300 us 1,3 Tfall Fall time of PD# and SRC_STOP# 5 ns 1 Trise Rise time of PD# and SRC_STOP# 5 ns 2 1Guaranteed by design and characterization, not 100% tested in production. 2See timing diagrams for timing requirements. 3Time from deassertion until outputs are >200 mV 0723D—01/08/04 DataSheet4 U .com 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9DB108 PD#, Power Down The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down. PD# Assertion When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated. PWRDWN# DIF DIF# PD# De-assertion Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion. PWRDWN# Tstable <1mS DIF DIF# Tdrive_PwrDwn# <300uS, >200mV 0723D—01/08/04 DataSheet4 U .com 11 11 Page

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