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PDF DS1972 Data sheet ( Hoja de datos )
| Número de pieza | DS1972 | |
| Descripción | 1024-Bit EEPROM iButton | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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DS1972
1024-Bit EEPROM iButton
www.maxim-ic.com
iButton DESCRIPTION
The DS1972 is a 1024-bit, 1-Wire® EEPROM
organized as four memory pages of 256 bits each in
a rugged iButton package. Data is written to an 8-
byte scratchpad, verified, and then copied to the
EEPROM memory. As a special feature, the four
memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only
be changed from a 1 to a 0 state. The DS1972
communicates over the single-conductor 1-Wire bus.
The communication follows the standard Dallas
Semiconductor 1-Wire protocol. Each device has its
own unalterable and unique 64-bit ROM registration
number that is factory lasered into the device. The
registration number is used to address the device in
a multidrop 1-Wire net environment.
APPLICATIONS
Access Control/Parking Meter
Work-In-Progress Tracking
Tool Management
Inventory Control
Maintenance/Inspection Data Storage
F5 AND F3 MicroCAN
F3 size F5 size
3.10 5.89
0.51 0.51
Branding
â
16.25
51 â 2D
0000006234FB
1-Wireâ
17.35
IO GND IO GND
Commands, Registers, and Modes are capitalized for
clarity.
IButton, 1-Wire, and MicroCAN are registered trademarks of Dallas
Semiconductor Corp.
SPECIAL FEATURES
§ 1024 Bits of EEPROM Memory Partitioned into
Four Pages of 256 Bits
§ Individual Memory Pages can be Permanently
Write Protected or Put in EPROM-Emulation
Mode ("Write to 0")
§ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
§ IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air, typical)
§ Reads and Writes Over a Wide Voltage Range of
2.8V to 5.25V from -40°C to +85°C
§ Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
COMMON iButton FEATURES
§ Unique Factory-Lasered 64-Bit Registration
Number Assures Error-Free Device Selection
and Absolute Traceability Because No Two Parts
are Alike
§ Built-In Multidrop Controller for 1-Wire Net
§ Chip-Based Data Carrier Stores Digital Identifi-
cation and Information, Armored in a Durable
Stainless-Steel Case
§ Data can be Accessed While Affixed to Object
§ Button Shape is Self-Aligning with Cup-Shaped
Probes
§ Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed onto its Rim
§ Presence Detector Acknowledges when Reader
First Applies Voltage
§ Designed to meet UL#913 (4th Edit.); Intrinsically
Safe Apparatus: Under Entity Concept for use in
Class I, Division 1, Group A, B, C, and D
Locations, contact Dallas Semiconductor for
certification schedule
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS1972-F5#
-40°C to 85°C F5 iButton
DS1972-F3#
-40°C to 85°C F3 iButton
# indicates RoHS complience
Contact factory lead-free compliance
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 23
REV: 083006
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Figure 2. Hierarchical Structure for 1-Wire Protocol
DS1972: 1024-Bit EEPROM iButton
DS1972 Command Level:
1-Wire ROM Function
Commands (see Figure 9)
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive-Skip
Overdrive-Match
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
DS1972-specific
Memory Function
Commands (see Figure 7)
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
64-bit Scratchpad, Flags
64-bit Scratchpad
Data Memory, Register Page
Data Memory, Register Page
64-BIT LASERED ROM
Each DS1972 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the
last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
MSB
8-Bit
CRC Code
MSB
LSB
MSB
48-Bit Serial Number
LSB
8-Bit Family
Code (2Dh)
LSB MSB
LSB
Figure 4. 1-Wire CRC Generator
Polynomial = X8 + X5 + X4 + 1
1st 2nd 3rd 4th
STAGE STAGE STAGE STAGE
X0 X1 X2 X3
5th
STAGE
X4
5 of 23
6th 7th 8th
STAGE STAGE STAGE
X5 X6
X7
INPUT DATA
X8
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Figure 7-3. Memory Function Flow Chart (continued)
DS1972: 1024-Bit EEPROM iButton
From Figure 7
2nd Part
55h
Copy Scratch-
Pad ?
N
Y
Bus Master TX
TA1 (T7:T0), TA2 (T15:T8)
and E/S Byte
Applicable to all R/W
memory locations.
To Figure 7
4th Part
Auth. Code
Match ?
Y
T15:T0
< 0090h ?
Y
NN
N
PF = 0 ?
Y
Y Copy-
Protected ?
N
AA = 1
Duration: tPROG
DS1972 copies Scratch-
pad Data to Address
*
DS1972 TX “0”
Bus Master
RX “1”s
Master
TX Reset ?
N
Y
To Figure 7
2nd Part
* 1-Wire idle high for power
Y Master
TX Reset ?
N
DS1972 TX “1”
Master
TX Reset ?
N
Y
From Figure 7
4th Part
11 of 23
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| PDF Descargar | [ Datasheet DS1972.PDF ] | |
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