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Integrated Device Technology - (IDT72V1x071) 3.3 VOLT DUAL MULTIMEDIA FIFO

Numéro de référence IDT72V12071
Description (IDT72V1x071) 3.3 VOLT DUAL MULTIMEDIA FIFO
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
FEATURES
Memory organization:
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Dual 256 x 8
Dual 512 x 8
Dual 1,024 x 8
Dual 2,048 x 8
Dual 4,096 x 8
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
15 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty and Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
Industrial temperature range (–40°C to +85°C)
DESCRIPTION
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (WENA, WENB). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (RENA, RENB). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(OEA, OEB) is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
DA0 - DA7
Data In
x8
WRITE
CONTROL
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
RSA
READ
CONTROL
FLAG OUTPUTS
EFA FFA
RCLKA
RENA
OEA
QA0 - QA7
Data Out
x8
WCLKB
WENB
DB0 - DB7
Data In
x8
WRITE
CONTROL
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
RSB
READ
CONTROL
RCLKB
RENB
OEB
QB0 - QB7
Data Out
x8
FLAG OUTPUTS
EFB FFB
6360 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DataSheet4 U .com
NOVEMBER 2003
DSC-6360/1

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