IDT72V11071 Datasheet PDF - Integrated Device Technology
| Part Number | IDT72V11071 | |
| Description | (IDT72V1x071) 3.3 VOLT DUAL MULTIMEDIA FIFO | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
FEATURES
• Memory organization:
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Dual 256 x 8
Dual 512 x 8
Dual 1,024 x 8
Dual 2,048 x 8
Dual 4,096 x 8
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• 15 ns read/write cycle time
• 5V input tolerant
• Separate control lines and data lines for each FIFO
• Separate Empty and Full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
• Industrial temperature range (–40°C to +85°C)
DESCRIPTION
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (WENA, WENB). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (RENA, RENB). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(OEA, OEB) is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
DA0 - DA7
Data In
x8
WRITE
CONTROL
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
RSA
READ
CONTROL
FLAG OUTPUTS
EFA FFA
RCLKA
RENA
OEA
QA0 - QA7
Data Out
x8
WCLKB
WENB
DB0 - DB7
Data In
x8
WRITE
CONTROL
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
RSB
READ
CONTROL
RCLKB
RENB
OEB
QB0 - QB7
Data Out
x8
FLAG OUTPUTS
EFB FFB
6360 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DataSheet4 U .com
NOVEMBER 2003
DSC-6360/1
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IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
AC ELECTRICAL CHARACTERISTICS(1)
(Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tSKEW1
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
INDUSTRIALTEMPERATURERANGE
Industrial
IDT72V10071L15
IDT72V11071L15
IDT72V12071L15
IDT72V13071L15
IDT72V14071L15
Min. Max.
— 66.7
2 10
15 —
6—
6—
4—
1—
4—
1—
15 —
10 —
10 —
— 15
0—
38
38
— 10
— 10
6—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
D.U.T.
510Ω
3.3V
330Ω
30pF*
6360 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
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| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT72V11071.PDF Datasheet ] | |
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