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PDF MC74LVXT4053 Data sheet ( Hoja de datos )

Número de pieza MC74LVXT4053
Descripción Analog Multiplexer/ Demultiplexer
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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MC74LVXT4053
Analog Multiplexer/
Demultiplexer
HighPerformance SiliconGate CMOS
The MC74LVXT4053 utilizes silicongate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The LVXT4053 is similar in pinout to the LVX8053, the HC4053A,
and the metalgate MC14053B. The ChannelSelect inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The ChannelSelect and Enable inputs are compatible with standard
TTL levels.
This device has been designed so the ON resistance (RON) is more
linear over input voltage than the RON of metalgate CMOS analog
switches and HighSpeed CMOS analog switches.
Features
Select Pins Compatible with TTL Levels
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Analog Power Supply Range (VCC VEE) = *3.0 V to )3.0 V
Digital (Control) Power Supply Range (VCC GND) = 2.5 to 6.0 V
Improved Linearity and Lower ON Resistance Than MetalGate,
HSL, or VHC Counterparts
Low Noise
Designed to Operate on a Single Supply with VEE = GND,
or Using Split Supplies up to ±3.0 V
BreakBeforeMake Circuitry
These Devices are PbFree and are RoHS Compliant
www.onsemi.com
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
VCC Y X X1 X0 A B
16 15 14 13 12 11 10
C
9
12345678
Y1 Y0 Z1 Z Z0 Enable VEE GND
MARKING DIAGRAMS
16
LVXT4053G
AWLYWW
1
SOIC16
16
LVXT
4053
ALYWG
G
1
TSSOP16
LVXT4053 = Specific Device Code
A = Assembly Location
WL, L
= Wafer Lot
Y = Year
WW, W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 7
1
Publication Order Number:
MC74LVXT4053/D

1 page




MC74LVXT4053 pdf
MC74LVXT4053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation Delay, ChannelSelect
to Analog Output
(Figures 15 and 16)
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog
Output (Figures 13 and 14)
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog
Output (Figures 13 and 14)
VCC
V
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
VEE
V
0
0
0
3.0
0
0
0
3.0
0
0
0
3.0
Guaranteed Limit
55 to 25°C
v85°C
Min Typ Max Min Max
40 45
28 30
23 25
23 25
40 45
28 30
23 25
23 25
40 45
28 30
23 25
23 25
v125°C
Min Max
50
35
30
28
50
35
30
28
50
35
30
28
Unit
ns
ns
ns
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 17) (Note 6)
45
CIN Maximum Input Capacitance, ChannelSelect or Enable Inputs
10
CI/O Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
10
10
1.0
6. Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
pF
pF
pF
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Condition
VCC VEE Typ
V V 25°C Unit
BW Maximum OnChannel Bandwidth or Minimum VIS = ½ (VCC VEE)
Frequency Response
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 6)
3.0 0.0 80 MHz
4.5 0.0 80
6.0 0.0 80
3.0 3.0 80
VISO OffChannel Feedthrough Isolation
f = 1 MHz; VIS = ½ (VCC VEE)
3.0 0.0 70 dB
Adjust Network Analyzer output to 10 dBm 4.5 0.0 70
on each output from the power splitter.
6.0 0.0 70
(Figures 7 and 8)
3.0 3.0 70
VONL Maximum Feedthrough On Loss
VIS = ½ (VCC VEE)
3.0 0.0 2 dB
Adjust Network Analyzer output to 10 dBm 4.5 0.0 2
on each output from the power splitter.
6.0 0.0 2
(Figure 10)
3.0 3.0 2
Q Charge Injection
VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 W, CL= 1000 pF, Q = CL * DVOUT
(Figure 9)
5.0 0.0 9.0 pC
3.0 3.0 12
THD Total Harmonic Distortion THD + Noise
fIS = 1 MHz, RL = 10 KW, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 18)
%
6.0 0.0 0.10
3.0 3.0 0.05
www.onsemi.com
5

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MC74LVXT4053 arduino
MC74LVXT4053
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = )5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swing is determined by the
supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is five volts. Therefore,
using the configuration of Figure 20, a maximum analog
signal of five volts peaktopeak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VEE GND = 0 to *6 volts
VCC GND = 2.5 to 6 volts
VCC VEE = 2.5 to 6 volts
and VEE v GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 21. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
+3.0 V
3.0 V
ANALOG
SIGNAL
+3.0 V
16
ON
ANALOG
SIGNAL
+3.0 V
3.0 V
+5 V
GND
ANALOG
SIGNAL
+5 V
16
ON
ANALOG
SIGNAL
+5 V
GND
3.0 V
6 11
7 10
89
TO EXTERNAL CMOS
CIRCUITRY 0 to 3.0 V
DIGITAL SIGNALS
Figure 19. Application Example
6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5 V
8 9 DIGITAL SIGNALS
Figure 20. Application Example
VCC
Dx
Dx
VEE
VEE
VCC
16
ON/OFF
VCC
Dx
Dx
VEE
7
8
Figure 21. External Germanium or Schottky Clipping Diodes
www.onsemi.com
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