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PDF MC74LVX8051 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX8051 | |
| Descripción | Analog Multiplexer/Demultiplexer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LVX8051
Analog Multiplexer /
Demultiplexer
High–Performance Silicon–Gate CMOS
The MC74LVX8051 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to GND).
The LVX8051 is similar in pinout to the high–speed HC4051A and
the metal–gate MC14051B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pull–up resistors they are compatible with
LSTTL outputs.
This device has been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: LVX8051 — 184 FETs or 46 Equivalent Gates
LOGIC DIAGRAM
MC74LVX8051
Single–Pole, 8–Position Plus Common Off
X0 13
X1 14
ANALOG
INPUTS/
OUTPUTS
X2 15
X3 12
X4 1
MULTIPLEXER/
DEMULTIPLEXER
X5 5
X6 2
X7 4
CHANNEL
SELECT
INPUTS
A 11
B 10
C9
ENABLE 6
PIN 16 = VCC
PIN 8 = GND
3
X
COMMON
OUTPUT/
INPUT
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16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC X2 X1 X0 X3 A B C
16 15 14 13 12 11 10 9
12345678
X4 X6 X X7 X5 Enable NC GND
For detailed package marking information, see the Marking
Diagram section on page 11 of this data sheet.
ORDERING INFORMATION
Device
Package
Shipping
MC74LVX8051D
SOIC
48 Units/Rail
MC74LVX8051DT
TSSOP
96 Units/Rail
FUNCTION TABLE – MC74LVX8051
Control Inputs
Enable
Select
CBA
ON Channels
L LLL
L LLH
L LHL
L LHH
L HLL
L HLH
L HHL
L HHH
H XXX
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
© Semiconductor Components Industries, LLC, 1999
October, 1999 – Rev. 1.0
DataSheet4 U .com
1
Publication Order Number:
MC74LVX8051/D
1 page  
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MC74LVX8051
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
BW Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
Condition
fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain
0dBm at VOS; Increase fin Frequency Until dB
Meter Reads –3dB;
RL = 50Ω, CL = 10pF
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm
(Figure 7)
at VIS
fin = 10kHz, RL = 600Ω, CL = 50pF
fin = 1.0MHz, RL = 50Ω, CL = 10pF
— Feedthrough Noise.
Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL
Channel–Select Input to Common at Setup so that IS = 0A;
I/O (Figure 8)
Enable = GND
RL = 600Ω, CL = 50pF
RL = 10kΩ, CL = 10pF
THD Total Harmonic Distortion
(Figure 14)
fin = 1kHz, RL = 10kΩ, CL = 50pF
THD = THDmeasured – THDsource
VIS = 2.0VPP sine wave
VIS = 4.0VPP sine wave
VIS = 5.0VPP sine wave
*Limits not tested. Determined by design and verified by qualification.
VCC
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
25
20 125°C
85°C
15 25°C
10 – 55°C
5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN, INPUT VOLTAGE (VOLTS)
Figure 1a. Typical On Resistance, VCC = 3.0 V
Limit*
25°C
80
80
80
–50
–50
–50
–37
–37
–37
25
105
135
35
145
190
0.10
0.08
0.05
Unit
MHz
dB
mVPP
%
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5
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MC74LVX8051
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10 9
LVX8051
AWLYWW*
12345678
16 15 14 13 12 11 10 9
LVX
8051
ALYW*
12345678
16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
*See Applications Note #AND8004/D for date code and traceability information.
–A
–
16
1
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
9
–B
–
8
P 8 PL
0.25 (0.010) M
BM
–T
SEAT–ING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
M
R X 45°
F
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G
1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
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