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PDF MC74LVX574 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX574 | |
| Descripción | LOW-VOLTAGE CMOS | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LVX574
Octal D−Type Flip−Flop
with 3−State Outputs
The MC74LVX574 is an advanced high speed CMOS octal
flip−flop with 3−state outputs. The inputs tolerate voltages up to 7.0 V,
allowing the interface of 5.0 V systems to 3.0 V systems.
This 8−bit D−type flip−flop is controlled by a clock pulse input and
an output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
Features
• High Speed: tPD = 8.5 ns (Typ) at VCC = 3.3 V
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Pb−Free Packages are Available*
www.DataSheet4U.com
VCC O0 O1 O2 O3 O4 O5 O6 O7 CP
20 19 18 17 16 15 14 13 12 11
http://onsemi.com
MARKING
DIAGRAMS
20
1
20
SOIC−20
DW SUFFIX
CASE 751D
1
LVX574
AWLYYWW
20
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
LVX
574
ALYW
20
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
74LVX574
AWLYWW
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 1. 20−Lead Pinout (Top View)
A
L, WL
Y, YY
W, WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 2
1
Publication Order Number:
MC74LVX574/D
1 page  
MC74LVX574
SWITCHING WAVEFORMS
CP 50%
tw
1/fmax
tPLH
tPHL
Q 50% VCC
VCC
GND
Figure 3.
OE
50%
tPZL tPLZ
O 50% VCC
tPZH tPHZ
O 50% VCC
Figure 4.
VCC
VOL +0.3V
GND
VOL −0.H3IVGH
IMPEDANCE
HIGH
IMPEDANCE
VALID
D 50%
tsu th
CP 50%
Figure 5.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
*Includes all probe and jig capacitance
Figure 7. Three−State Test Circuit
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74LVX574.PDF ] | |
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