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PDF MC74LVX373 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX373 | |
| Descripción | LOW-VOLTAGE CMOS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D-Type Latch
with 3-State Outputs
With 5V-Tolerant Inputs
The MC74LVX373 is an advanced high speed CMOS octal latch with
3–state outputs. The inputs tolerate voltages up to 7V, allowing the
interface of 5V systems to 3V systems.
This 8–bit D–type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
• High Speed: tPD = 5.8ns (Typ) at VCC = 3.3V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
MC74LVX373
LVX
LOW–VOLTAGE CMOS
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. 20–Lead Pinout (Top View)
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
6/97
© Motorola, Inc. 1997
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TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
tw(h)
Parameter
Minimum Pulse Width, LE
tsu Minimum Setup Time, D to LE
th Minimum Hold Time, D to LE
MC74LVX373
Test Conditions
VCC = 2.7V
VCC = 3.3 ±0.3V
VCC = 2.7V
VCC = 3.3 ±0.3V
VCC = 2.7V
VCC = 3.3 ±0.3V
TA = 25°C
Typ Limit
6.5
5.0
6.0
4.0
1.0
1.0
TA = – 40
to 85°C
Limit
7.5
5.0
6.0
4.0
1.0
1.0
Unit
ns
ns
ns
D 50%
tPLH
O 50% VCC
SWITCHING WAVEFORMS
VCC
GND
tPHL
tw
LE 50%
tPLH
O 50% VCC
tPHL
VCC
GND
Figure 3.
Figure 4.
OE
O
O
50%
tPZL tPLZ
50% VCC
tPZH tPHZ
50% VCC
Figure 5.
VCC
GND
HIGH
IMPEDANCE
VOL +0.3V
VOL –0.3V
HIGH
IMPEDANCE
D
LE
TEST CIRCUITS
VALID
50%
tsu th
50%
Figure 6.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 7. Propagation Delay Test Circuit
* Includes all probe and jig capacitance
Figure 8. Three–State Test Circuit
LCX DATA
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MOTOROLA
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| PDF Descargar | [ Datasheet MC74LVX373.PDF ] | |
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