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PDF NJW1148 Data sheet ( Hoja de datos )
| Número de pieza | NJW1148 | |
| Descripción | Audio Processor | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJW1148
Audio Processor with Sound Enhancement and TruSurround Virtualizer
I GENERAL DESCRIPTION
The NJW1148 is an audio processor with BBE sound enhancement
and SRS Labs' TruSurround virtualizer. It includes all of functions
processing audio signal for TV, such as volume, balance, mute, line out,
tone control, eala NJRC surround and simulated stereo functions. All of
internal status and variables are controlled by I2C BUS.
I FEATURES
I PACKAGE OUTLINE
G Operating Voltage
8 to 10 V
G I2C BUS Interface
(Fast-Mode)
G Passive TruSurround
G BBE
0dB to +15dB(0.5dB/step)
G eala (surround effect ; 2 steps) and Simulated Stereo
GVolume
0 to -80dB, MUTE(0.33dB/step)
GBalance
0 to -30dB, MUTE(1dB/step)
GTone Control
-15dB to +15dB(0.5dB/step)
G Bi-CMOS Technology
G Package Outline
QFP48-P1
NJW1148FP1
I BLOCK DIAGRAM
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DataShee
INA VOL1
BBE
TONE
VOL2
Passive Matrix
TruSurround
/ SRS 3D Stereo
/ eala
VOL2
/ Simulated Stereo
INB VOL1
BBE
TONE
VOL2
AGCTC
Bias
Buffer
VREF
MIXOUT
LFIN
LFOUT
OUTC
CAP
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NJW1148
et4U.com
I I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYMBOL MIN. TYP. MAX. UNIT
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
Hysteresis of Schmitt trigger inputs
Vhys
LOW level output voltage (3mA at SDA pin)
VOL
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
tof
Pulse width of spikes which must be suppressed by the input filter
tSP
Input current each I/O pin with an input voltage between 0.1VDD
and 0.9VDDmax
Ii
Capacitance for each I/O pin
Ci
SCL clock frequency
fSCL
Hold time (repeated) START condition.
tHD:STA
LOW period of the SCL clock
tLOW
HIGH period of the SCL clock
tHIGH
Set-up time for a repeated START condition
tSU:STA
Data hold time
tHD:DAT
Data set-up time
tSU:DAT
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
tr
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Set-up time for STOP condition
tSU:STO
Bus free time between a STOP and START condition
tBUF
Capacitive load for each bus line
Cb
Noise margin at the LOW level
VnL
Noise margin at the HIGH level
VnH
0.0 -
3.0 -
0.25 -
0-
1.5
5.0
-
0.4
V
V
V
V
20+0.1Cb
-
250
ns
0 - 50 ns
-10 - 10 µA
- - 10 pF
- - 400 kHz
0.6 - - µs
1.3 - - µs
0.6 - - µs
0.6 - - µs
- - 0.9 µs
100 - - ns
- - 300 ns
- - 300 ns DataShee
0.6 - - µs
1.3 - - µs
- - 400 pF
0.5 -
-
V
1--
V
Cb ; total capacitance of one bus line in pF.
SDA
tf tr
SCL
tHD:STA
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
ttSP
tBUF
r
tSU:STO
P
S
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PIN
NO.
SYMBOL
FUNCTION
21 VREF Reference Voltage
Stabilizing Capacitor
NJW1148
EQUIVALENT CIRCUIT
TERMINAL
VOLTAGE
21 V+/2
22 TONEHTC Tone Control Treble
Switching Noise
Rejection Capacitor
23 TONELTC Tone Control Bass
Switching Noise
Rejection Capacitor
22,23
36k
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24 OUTTC Line Output switching
Noise Rejection
Capacitor
36k
24
Vref-0.7V
(Tone=FLAT)
DataShee
5V
(OUT-ON)
25 BBELTC BBE Low Switching
Noise Rejection
Capacitor
36k
25
Vref-0.7V
(BBE=ON)
(Low=0dB)
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| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet NJW1148.PDF ] | |
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