PDF IDTCV104B Data sheet ( Hoja de datos )

Número de pieza	IDTCV104B
Descripción	CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
Fabricantes	Integrated Device Technology
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Hay una vista previa y un enlace de descarga de IDTCV104B (archivo pdf) en la parte inferior de esta página. Total 21 Páginas
No Preview Available ! www.DataSheet4U.com IDTCV104B CLOCKGENERATORFORDESKTOPPCPLATFORMS CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIALTEMPERATURERANGE IDTCV104B PRELIMINARY FEATURES: • 4 PLL architecture • Linear frequency programming • Independent frequency programming and SSC control • Band-gap circuit for differential output • High power-noise rejection ratio • 66MHz to 533MHz CPU frequency • VCO frequency up to 1.1G • Support index block read/write, single cycle index block read • Programmable REF, 3V66, PCI, 48MHz I/O drive strength • Programmable 3V66 and PCI Skew • Available in SSOP package DESCRIPTION: IDTCV104B is a 48 pin clock generation device for desktop PC platforms. This chip incorporates four PLLs to allow independent generation of CPU, AGP/ PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, providing high accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread Spectrum selection. KEY SPECIFICATION: • CPU/SRC CLK cycle to cycle jitter < 125ps • SATA CLK cycle to cycle jitter < 125ps • PCI CLK cycle to cycle jitter < 250ps • Static PLL frequency divide error as low as 36ppm FUNCTIONAL BLOCK DIAGRAM X1 XTAL Osc Amp X2 DataSheet4U.com PLL1 SSC EasyN Programming CPU CLK Output Buffers IREF SDATA SCLK SM Bus Controller PLL2 SSC EasyN Programming 3V66/PCI Output Buffers CPU[1:0] REF 3.1.0 PCI[5:0], PCIF[2:0] 3V66[3:0] DataShee VTT_PWRGD FS[1:0] SEL24_48# Watch Dog Timer Control Logic PLL3 SSC PLL4 SRC CLK Output Buffer IREF 48MHz Output Buffer SRC 48MHz[1:0] 24 - 48MHz RESET# OUTPUT TABLE CPU (Pair) 3V66 3V66/VCH PCI PCIF 2 3 1 63 DataSheet4U.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE © 2003 Integrated Device Technology, Inc. REF 3 1 48MHz 2 24 - 48MHz 1 SRC (Pair) 1 Reset# 1 SEPTEMBER 2003 DSC-6382/16 1 page www.DataSheet4U.com IDTCV104B CLOCKGENERATORFORDESKTOPPCPLATFORMS COMMERCIALTEMPERATURERANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 41 VDD_CPU PWR 42 CPUC1 OUT 43 CPUT1 OUT 44 VSS GND 45 IREF OUT 46 VSS GND 47 VDDA PWR 48 REF3 OUT 3.3V Hosts 0.7V current mode differential clock output Hosts 0.7V current mode differential clock output GND Reference current for differential clock output GND 3.3V 14.318 MHz reference clock output Description et4U.com DataSheet4U.com DataShee DataSheet4U.com 5 5 Page www.DataSheet4U.com IDTCV104B CLOCKGENERATORFORDESKTOPPCPLATFORMS BYTE 26: CPU PLL CONTROL Bit Output(s)Affected Description/Function 7 WDBS2 At the event of WD hard alarm time out, 6 WDBS1 If Byte 32 bit 7 = 1, CPU frequency is 5 WDBS0 selected by WDBS[2:0] WDCFS[2:0](1) 4 CSMC2 CPU SMC2, SMC table 3 CSMC1 CPU SMC1, SMC table 2 CSMC0 CPU SMC0, SMC table 1 CPN9 CPU PLL N9 0 CPN8 CPU PLL N8 NOTE: 1. See SW FREQUENCY SELECTION table. COMMERCIALTEMPERATURERANGE 0 1 Type Power On RW 1 RW 0 RW 0 RW 0 RW 1 RW 0 RW RW BYTE 27: CPU PLL N PROGRAMMING In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN[9:0] range is 290 - 600. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N driver. See SW FREQUENCY SELECTION table. Bit Output(s)Affected Description/Function 0 1 Type Power On 7 CPN7 CPU PLL N7 RW 6 CPN6 CPU PLL N6 RW et4U.com 5 4 3 CPN5 CPN4 CPN3 CPU PLL N5 CPU PLL N4 DaCtaPSUhPeLeL tN43U.com RW DataShee RW RW 2 CPN2 CPU PLL N2 RW 1 CPN1 CPU PLL N1 RW 0 CPN0 CPU PLL N0 RW BYTE 28: AGP/PCI PLL CONTROL Bit Output(s)Affected Description/Function 7 AFS2 See AGP/PCI FREQUENCY SELECTION table 6 AFS1 See AGP/PCI FREQUENCY SELECTION table 5 AFS0 See AGP/PCI FREQUENCY SELECTION table 4 WDAFS2 AGP/PCI WD hard alarm time out frequency selection 3 WDAFS1 AGP/PCI WD hard alarm time out frequency selection 2 WDAFSO AGP/PCI WD hard alarm time out frequency selection 1 APN9 AGP/PCI PLL N9 0 APN8 AGP/PCI PLL N8 0 1 Type Power On RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW RW DataSheet4U.com 11 11 Page

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