PDF IDT74LVC827A Data sheet ( Hoja de datos )

Número de pieza	IDT74LVC827A
Descripción	3.3V CMOS 10-BIT BUFFER/DRIVER
Fabricantes	Integrated Device Technology
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No Preview Available ! www.DataSheet4U.com IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O INDUSTRIALTEMPERATURERANGE IDT74LVC827A FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static) • Rail-to-rail output swing for increased noise margin • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SOIC, SSOP, QSOP, and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise DESCRIPTION: This 10-bit buffer/driver is built using advanced CMOS technology. The LVC827A device provides a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The LVC827A provides true data at its outputs. The LVC827A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DataSheet4U.com FUNCTIONAL BLOCK DIAGRAM DataShee OE1 OE2 1 13 A1 2 23 Y1 TO NINE OTHER CHANNELS DataSheet4U.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 1999 Integrated Device Technology, Inc. 1 OCTOBER 1999 DSC-4647/1 1 page www.DataSheet4U.com IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 6 VIH 2.7 2.7 VT 1.5 1.5 VLZ 300 300 VHZ 300 300 CL 50 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF VCC VLOAD Open VIN Pulse (1, 2) Generator VOUT D.U.T. 500Ω GND RT 500Ω CL Test Circuit for All Outputs LVC Link SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL Propagation Delay VIH VT 0V VOH VT VOL VIH VT 0V LVC Link CONTROL INPUT ENABLE tPZL DISABLE tPLZ OUTPUT NORMALLY LOW SWITCH VLOAD tPZH OUTPUT SWITCH NORMALLY GND HIGH VLOAD/2 VT tPHZ VT 0V VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V et4U.comDEFINITIONS: LVC Link CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse GeneratDor.ataSheetN4OUTE.c: om Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. DataShee SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open INPUT OUTPUT 1 OUTPUT 2 tPLH1 tPHL1 tSK (x) tSK (x) VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) LVC Link DataSheN1e.OtT4EFUoSr:.ctSoK(mo) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH tREM tSU tH Set-up, Hold, and Release Times VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V LVC Link LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE Pulse Width VT VT LVC Link 5 5 Page

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