|
|
PDF ICS9169C-273 Data sheet ( Hoja de datos )
| Número de pieza | ICS9169C-273 | |
| Descripción | Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS9169C-273 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9169C-273
Frequency Generator for Pentium™ Based Systems
General Description
Features
The ICS9169C-273 is a low-cost frequency generator
designed specifically for Pentium based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL crystal provides the
reference clock to generate standard Pentium frequencies.
The CPU clock makes gradual frequency transitions without
violating the PLL timing of internal microprocessor clock
multipliers.
Twelve CPU clock outputs provide sufficient clocks for the
CPU, chip set, memory and up to two DIMM connectors (with
four clocks to each DIMM). Either synchronous (CPU/2) or
asynchronous (32 MHz) PCI bus operation can be selected
by latching data on the BSEL input.
Block Diagram
• Twelve selectable CPU clocks operate up to 83.3MHz
• Maximum CPU jitter of ± 200ps
• Six BUS clocks support sync or async bus operation
• 250ps skew window for CPU outputs, 500ps skew
window for BUS outputs
• CPU clocks BUS clocks skew 0-2ns (CPU early)
• Integrated buffer outputs drive up to 30pF loads
• 3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.375-
2.62V) VDD option
• 32-pin SOJ package
• Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
• 48 MHz clock for USB support and 24 MHz clock for FD
Pin Configuration
DataSheet4U.com
DataShee
VDD Groups:
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU(1:6)
VDD3 = CPU(7:12) & PLL Core
VDD4 = BUS(1:6)
VDD5 = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
DataSheet4U.com
9169C-273RevC031897
32-Pin SOJ
ADDRESS
SELECT
FS2 FS1 FS0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
CPU(1:12)
(MHz)
50
60
66.6
REF/2
55
75
83.3
Tristate
BUS (1:6)MHz
BSEL=1
25
30
33.3
REF/4
27.5
37.5
41.7
Tristate
BSEL=0
32
32
32
REF/3
32
32
32
Tristate
48MHz
48
48
48
REF/2
48
48
48
Tristate
24MHz
24
24
24
REF/4
24
24
24
Tristate
REF
REF
REF
REF
REF
REF
REF
REF
Tristate
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
1 page  
www.DataSheet4U.com
ICS9169C-273
Technical Pin Function Descriptions
et4U.com
VDD1
This is the power supply to the internal logic of the device as clocks is controlled by the supply that is applied to the
well as the following clock output buffers:
VDD pin of the group. See the Functionality Table at the
beginning of this data sheet for a list of the specific
A. REF clock output buffers
B. BUS clock output buffers
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
C. Fixed clock output buffers
FS0, FS1, FS2
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
These pins control the frequency of the clocks at the CPU,
CPUL, BUS & SDRAM pins. See the Funtionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies. The
device reads these pins at power-up and stores the
programmed selection code in an internal data latch. (See
GND
This is the power supply ground return pin for the internal
programming section of this data sheet for configuration
circuitry recommendations.
logic of the device as well as the following Clock Output
buffers:
BSEL
When this pin is a logic 1, it will place the CPU clocks in
the synchronous mode (running at half the frequency of
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
D. Fixed clock output buffers
E. 24/48MHz clock output buffers
the Ref). If this pin is a logic 0, it will be in the asynchronous
mode for the CPU clocks and will operate at the
preprogrammed fixed frequency rate. It is a shared pin
DataSheet4Uan.dcoims programed the same way as the frequency select
pins.
DataShee
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, X1 is the device’ input
pin for that reference clock. This pin also implements an
internal crystal loading capacitor that is connected to ground.
See the data tables for the value of the capacitor.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is
an output signal that drives (or excites) the discrete crystal.
This pin also implements an internal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
CPU (1:12)
These pins are clock outputs that drive the processor and
other CPU related circuitry that require clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these clocks is controlled by that which is applied
to the VDD pins of the device. See note on VDD3. See the
Functionality Table at the beginning of this data sheet for
a list of the specific frequencies that this clock operates at
and the selection codes that are necessary to produce
these frequencies.
BUS (1:6)
These pins are the Clock Outputs that are intended to drive
DataSheet4Uth.ceosmystems plug-in card bus. The voltage swing of these
VDD (2:3)
These are the power supply pins for the CPU (1:6) and
CPU (7:12) clock buffers. By separating the clock power
pins, each group can receive the appropriate power
decoupling and bypassing necessary to minimize EMI
and crosstalk between the individual signals. VDD2 can
be reduced to 2.5V VDD for advanced processor clocks,
which will bring CPU (1:6) outputs at 0 to 2.5V output
swings.
VDD4
This is the power supply pin for BUS clock buffers
BUS (1:6).
VDD5
This is the power supply pin for fixed clock buffer (48MHz
and 24MHz).
48 MHz
This is a fixed frequency clock that is typically used to
drive Super I/O peripheral device needs.
24 MHz
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ICS9169C-273.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS9169C-27 | Frequency Generator for Pentium Based Systems | Integrated Circuit Systems |
| ICS9169C-271 | Frequency Generator | Integrated Circuit Systems |
| ICS9169C-272 | Frequency Generator | Integrated Circuit Systems |
| ICS9169C-273 | Frequency Generator | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |