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PDF ICS9169C-271 Data sheet ( Hoja de datos )
| Número de pieza | ICS9169C-271 | |
| Descripción | Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9169C-271
Frequency Generator for Pentium™ Based Systems
General Description
Features
The ICS9169C-271 is a low-cost frequency generator
designed specifically for Pentium based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL oscillator provides
the reference clock to generate standard Pentium frequencies.
The CPU clock makes gradual frequency transitions without
violating the PLL timing of internal microprocessor clock
multipliers. A raised frequency setting of 68.5MHz is available
for Turbo-mode of the 66.8MHz CPU. The ICS9169C-271
contains 12 CPU clocks, 4 PCI clocks, 1 REF at 48MHz and 1 at
24MHz.
•
•
•
•
•
•
•
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•
The twelve CPU clock outputs provide sufficient clocks for
the CPU, chip set, memory and up to two DIMM connectors
(with four clocks to each DIMM). Either synchronous(CPU/
2) or asynchronous (32 MHz) PCI busoperation can be selected
by latching data on the BSEL input.
•
Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of ± 200ps
Six BUS clocks support sync or async bus operation
±250ps skew for all synchronous clock edges
CPU clocks BUS clocks skew 1-4ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:12) outputs
2.5V(2.375-2.62V) VDD option
32-pin SOIC/SOJ package
Logic inputs latched at Power-On for frequency
selection saving pins as Input/Output
48 MHz clock for USB support and 24 MHz clock
for FD.
Pin Configuration
Block Diagram
DataShee
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VDD Groups:
VDD = X1, X2, REF/BSEL
VDDC1 = CPU1-6
VDDC2 = CPU7-12 & PLL Core
VDDB = BUS1-6
VDDF = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
DataSheet4UL.4co=mFS2
9169C-271RevC060297P
32-Pin SOIC/SOJ
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
ADDRESS
SELECT
FS2 FS1 FS0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CPU(1:12)
(MHz)
50
60
66.8
75.9
55
75.9
83.3
68.5
BUS (1:6)MHz
BSEL=1
25
30
33.4
32
27.5
37.5
41.7
34.25
BSEL=0
32
32
32
32
32
32
32
32
48MHz
48
48
48
48
48
48
48
48
24MHz
24
24
24
24
24
24
24
24
REF
REF
REF
REF
REF
REF
REF
REF
REF
Pentium is a trademark of Intel Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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ICS9169C-271
Technical Pin Function Descriptions
et4U.com
VDD
clocks is control-led by the supply that is applied to the
This is the power supply to the internal logic of the device as VDD pin of the device. See the Functionality table at the
well as the following clock output buffers:
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
A. REF clock output buffers
codes that are necessary to produce these frequencies.
B. BUS clock output buffers
C. Fixed clock output buffers
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
This pin may be operated at any voltage between 3.0 and 5.5 CPUL, BUS & SDRAM pins. See the Funtionality table at
volts. Clocks from the listed buffers that it supplies will the beginning of this data sheet for a list of the specific
have a voltage swing from ground to this level. For the frequencies that this clock operates at and the selection
actual guaranteed high and low voltage levels of these codes that are necessary to produce these frequencies. The
clocks, please consult the AC parameter table in this data device reads these pins at power-up and stores the
sheet.
programmed selection code in an internal data latch. (See
programming section of this data sheet for configuration
GND
circuitry recommendations.
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output BSEL
buffers:
This pin controls whether the BUS clocks will be synchronous
(run at half the frequency) with the CPU and CPUL clocks or
A. REF clock output buffers
whether they will be asynchronous (run at a pre-programmed
B. BUS clock output buffers
fixed frequency) clock rate. It is a shared pin and is pro
C. CPU clock output buffers
D. Fixed clock output buffers
grammed the same way as the frequency select pins.
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VDDC (1:2)
X1 These are the power supply pins for the CPU (1:6) and CPU
This pin serves one of two functions. When the device is (7:12) clock buffers. By separating the clock power pins,
used with a crystal, X1 acts as the input pin for the reference each group can receive the appropriate power decoupling
signal that comes from the discrete crystal. When the device and bypassing necessary to minimize EMI and crosstalk
is driven by an external clock signal, X1 is the device’ input between the individual signals. VDDC1 can be reduced to
pin for that reference clock. This pin also implements an 2.5V VDD for advanced processor clocks, which will bring
internal crystal loading capacitor that is connected to ground. CPU (1:6) outputs at 0 to 2.5V output swings.
See the data tables for the value of the capacitor.
48 MHz
X2 This is a fixed frequency clock that is typically used to drive
This pin is used only when the device uses a Crystal as the Super I/O peripheral device needs.
reference frequency source. In this mode of operation, X2 is
an output signal that drives (or excites) the discrete crystal. 24 MHz
This pin also implements an internal crystal loading capacitor This is a fixed frequency clock that is typically used to drive
that is connected to ground. See the data tables for the value Keyboard controller clock needs.
of the capacitor.
REF
CPU This is a fixed frequency clock that runs at the same frequency
This pin is the clock output that drives processor and other as the input reference clock (typically 14.31818 MHz) is
CPU related circuitry that require clocks which are in tight and typically used to drive Video and ISA BUS
skew tolerance with the CPU clock. The voltage swing of requirements.
these clocks is controlled by that which is applied to the
VDDC pins of the device. See note on VDDC (1:2). See the VDDB
Functionality table at the beginning of this data sheet for a This power pin supplies the BUS clock buffers.
list of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these VDDF
frequencies.
This power pin supplies the 48/24 MHz clocks.
DataShee
BUS
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
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