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PDF ICS9160-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS9160-03 | |
| Descripción | Frequency Generator and Integrated Buffer for PowerPC | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9160-03 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9160-03
Preliminary Product Preview
Frequency Generator and Integrated Buffer for PowerPC®
General Description
The ICS9160-03 generates all clocks required for high speed
RISC microprocessor systems based on the PowerPC 603 and
604. Five different frequency multiplying factors are selectable
and offer smooth frequency transitions. BCLK signals are
synchronous to PCLK and operate at PCLK/2 for optimum
synchronous PCI bus performance. The multiplying and ratio
factors can be customed for specific applications.
Both individual and group glitch-free stop and start ofthe
clock signals are provided, as well as a power-down mode to
mize power consumption. The individual stop and start is
provided through a serial interface control.
A global output enable pin simplifies production board testing,
and a test mode is available to aid in system design and
diagnostics.
Features
• Generates four processor and seven synchronous
bus clocks plus graphic, floppy, keyboard and
reference clocks
• Selectable 33.3/50/60/66.6/80 MHz PCLKs
• ±150ps maximum PowerPC PLL in-band jitter
• All synchronous clocks skew matched to ±250ps
• Individual or group stop-clock control
• Power-down modes minimize standby current
• Custom configurations available
• 3.0V - 5.5 supply range
• 32-pin SOIC package
Pin Configuration
DataSheet4U.com
DataShee
Block Diagram
28-Pin SOIC
DataSheet4U.com
9160-03 RevC 06/19/97P
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
1 page  
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ICS9160-03
Preliminary Product Preview
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V
PARAMETER
Rise Time
Fall Time
Rise Time
Fall Time
Duty Cycle
Jitter, One Sigma
Jitter, Absolute
Jitter, One Sigma
et4U.com
Jitter, Absolute
Input Frequency
Clock Skew
Clock Skew
Clock Skew
SYMBOL
Tr1
Tf1
Tr1
Tf1
Dt1
Tj1s1
Tjab1
Tj1s1
Tjab1
Fi1
Tsk1
Tsk1
Tsk1
AC Characteristics
TEST CONDITIONS
20pF load, 0.8 to 2.0V
20pF load, 2.0 to 0.8V
20pF load, 20% to 80%
20pF load, 80% to 20%
20pF load
PCLK & BCLK Clocks; Load=20pF,
FOUT>25 MHz
PCLK & BCLK Clocks; Load=20pF,
FOUT>25 MHz
Fixed CLK and BCLK < 25 MHz and Fixed
CLK; Load=20pF
Fixed CLK and BCLK < 25 MHz;
Load=20pF
PCLK to PCLK; LDoaadt=a2S0hpFe;e@t41U.4.Vcom
BCLK0 to other BCLK; Load=20pF; @1.4V
PCLK to BCLK; Load=20pF; @1.4V
MIN
-
-
-
-
40
-
-250
-3.0
-5.0
-
-250
-500
1
TYP
1.5
0.9
2
1.8
50
50
-
1
2
14.318
50
90
2.6
MAX
3
2
4.5
4.25
60
150
250
3.0
5.0
-
250
500
5
UNITS
ns
ns
ns
ns
%
ps
ps
%
%
MHz
ps
ps
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: Jitter spectrum meets PowerPC PLL natural frequency in-band requirements of less than ±150ps.
DataShee
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICS9160-03.PDF ] | |
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