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PDF M58LR128FB Data sheet ( Hoja de datos )
| Número de pieza | M58LR128FB | |
| Descripción | Flash Memory | |
| Fabricantes | ST Microelectronics | |
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M58LR128FT
M58LR128FB
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Package
– VDD = 1.7V to 2.0V for program, erase and
read
– VDDQ = 1.7V to 2.0V for I/O Buffers
– VPP = 9V for fast program (12V tolerant)
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
FBGA
– Asynchronous Page Read mode
– Random Access: 85, 95ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Program
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array: 8 Mbit
Banks
– Parameter Blocks (Top or Bottom DataSheet4U.com
location)
VFBGA56 (ZB)
7.7 x 9mm
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code: 88C4h.
– Bottom Device Code: 88C5h
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
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M58LR128FT, M58LR128FB
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19.VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Bottom View Package Outline. . . . 52
Table 26. VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data. . . . . . . 52
Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 53
Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 54
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Top Boot Block Addresses, M58LR128FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30. Bottom Boot Block Addresses, M58LR128FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 34. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 35. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 37. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 38. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 39. Bank and Erase Block RegionDa1taInSfohremeat4tiUo.nc.o.m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 40. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 23.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 24.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 70
Figure 25.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 26.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 27.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 28.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 74
Figure 29.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 75
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 41. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 42. Command Interface States - Modify Table, Next Output State . . . . . . . . . . . . . . . . . . . . 78
Table 43. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 44. Command Interface States - Lock Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 80
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 45. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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M58LR128FT, M58LR128FB
should be as close as possible to the pack-
age). See Figure 9., AC Measurement Load Cir-
cuit. The PCB trace widths should be sufficient
to carry the required VPP program and erase
currents.
BUS OPERATIONS
There are six standard bus operations that control the Latch Enable should be tied to VIH during the
the device. These are Bus Read, Bus Write, Ad- bus write operation.
dress Latch, Output Disable, Standby and Reset.
See Table 3., Bus Operations, for a summary.
See Figures 16 and 17, Write AC Waveforms, and
Tables 23 and 24, Write AC Characteristics, for
Typically glitches of less than 5ns on Chip Enable details of the timing requirements.
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
Bus Read. Bus Read operations are used to out- able must be at VIL during address latch opera-
put the contents of the Memory Array, the Elec- tions. The addresses are latched on the rising
tronic Signature, the Status Register and the edge of Latch Enable.
Common Flash Interface. Both Chip Enable and Output Disable. The outputs are high imped-
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 10, 11, 12 and 13 Read AC Wave-
forms, and Tables 21 and 22 Read AC Character-
istics, for details of when the output becomes
valid.
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in standby when
Chip Enable and Reset are at VIH. The power con-
sumption is reduced to the standby level IDD4 and
the outputs are set to high impedance, indepen-
dently from the Output Enable or Write Enable in-
puts. If Chip Enable switches to VIH during a
program or erase operation, the device enters
Bus Write. Bus Write operations write Com- Standby mode when finished.
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Table 3. Bus Operations
Operation
E G W L RP
Bus Read
Bus Write
VIL VIL VIH VIL(2) VIH
VIL VIH VIL VIL(2) VIH
Address Latch
VIL X VIH VIL VIH
Output Disable
VIL VIH VIH X VIH
Standby
VIH X X X VIH
Reset
X X X X VIL
Note: 1. X = Don't care.
2. L can be tied to VIH if the valid address has been previously latched.
3. Depends on G.
4. WAIT signal polarity is configured using the Set Configuration Register command.
WAIT(4)
DQ15-DQ0
Data Output
Data Input
Data Output or Hi-Z (3)
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
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