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M36P0R9070E0 fiches techniques PDF

ST Microelectronics - Multi-Chip Package

Numéro de référence M36P0R9070E0
Description Multi-Chip Package
Fabricant ST Microelectronics 
Logo ST Microelectronics 





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M36P0R9070E0 fiche technique
www.DataSheet4U.com
M36P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory
128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
PRELIMINARY DATA
Features summary
Multi-chip package
– 1die of 512 Mbit (32Mb x 16, Multiple Bank,
Multi-Level, Burst) Flash Memory
– 1 die of 128Mbit (8Mb x16) PSRAM
FBGA
Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95V
– VPPF = 9V for fast program (12V tolerant)
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
Package
– ECOPACK®
TFBGA107 (ZAC)
Security
– 2112-bit user programmable OTP Cells
– 64-bit unique device number
100,000 program/erase cycles per block
Flash memory
Synchronous / asynchronous read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 93ns
Programming time
Block locking
– All Blocks locked at power-up
DataSheet4U.comAny combination of Blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
Common Flash Interface (CFI)
– 4µs typical Word program time using Buffer
Enhanced Factory Program command
PSRAM
Access time: 70ns
Memory organization
– Multiple Bank Memory Array: 64 Mbit
Banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent read within page: 20ns
Low power features
– Partial Array Self Refresh (PASR)
– Deep Power-Down mode (DPD)
Synchronous Burst Read/Write
– No delay between read and write
operations
DataShee
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
DataSheet4U.com
Rev. 1
1/26
www.st.com
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