NT5DS16M8AT Datasheet PDF - Nanya Techology
| Part Number | NT5DS16M8AT | |
| Description | (NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM | |
| Manufacturers | Nanya Techology | |
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NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR266A
(-7K)
DDR266B
(-75B)
DDR200
(-8B)
2 133 100
2.5 143 133
* Values are nominal (exact tCK should be used).
100
125
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 15.6µs Maximum Average Periodic Refresh
Interval
• Supports tRAS lockout feature
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• -7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
Read or Write command are used to select the bank and the
random-access memory containing 134,217,728 bits. It is
starting column location for the burst access.
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
The 128Mb DDR SDRAM uses a double-data-rate arcDhaitetacS- heet4bUur.sctolmengths of 2, 4 or 8 locations. An Auto Precharge func-
ture to achieve high-speed operation. The double data rate
tion may be enabled to provide a self-timed row precharge
DataShee
architecture is essentially a 2n prefetch architecture with an
that is initiated at the end of the burst access.
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
at the I/O pins.
An auto refresh mode is provided along with a power-saving
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL
Enabled mode of operation.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
DataSheetR4UE.Vco1m.0
May, 2001
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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www.DataSheet4U.com
NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Block Diagram (32Mb x 4)
et4U.com
CKEn
CK
CK
CSn
WE
CAS
RAS
Mode
Registers
12
12
A0-A11,
BA0, BA1
14
2
2
11 Column-Address
Counter/Latch
QFC
generator
DRVR
QFC
(Optional)
Bank1 Bank2 Bank3
Clk
DLL
4096
Bank0
Memory
Array
(4096 x 1024 x 8)
4
Data
Sense Amplifiers
8
4
4
DQS
1
Generator
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
COLo Input
DQS
8 Register
Write Mask 1
8
FIFO
&
21
Drivers
84
clk
out
cilnk
4
Data
1
1
1
4
4
4
Clk COLo
COLo
1
DataSheet4U.com
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
DataShee
DataSheetR4UE.Vco1m.0
May, 2001
DataSheet4 U .com
5
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for NT5DS16M8AT electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ NT5DS16M8AT.PDF Datasheet ] | |
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