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PDF NT5DS64M4CT Data sheet ( Hoja de datos )
| Número de pieza | NT5DS64M4CT | |
| Descripción | (NT5DSxxMxCx) 256Mb SDRAM | |
| Fabricantes | Nanya Techology | |
| Logotipo |  |
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NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
Features
CAS Latency and Frequency
CAS
Latency
Maximum Operating Frequency
(MHz)
DDR400
(5T)
DDR333
(6K/6KL)
2-
133
2.5 166
166
3 200
-
• DDR 256M bit, die C, based on 110nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2/2.5(DDR333) , 2.5/3(DDR400)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.5V ± 0.2V (DDR333)
• VDD = VDDQ = 2.6V ± 0.1V (DDR400)
• Available in Halogen and Lead Free packaging
Description
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT,
Read or Write command are used to select the bank and the
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS, and
starting column location for the burst access.
NT5DS16M16CG are die C of 256Mb SDRAM devices based
using DDR interface. They are all based on Nanya’s 110 nm The DDR SDRAM provides for programmable Read or Write
design process.
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
The
256Mb
DDR
SDRAM
uses
a
double-data-rate
arcDhaitteacS- heet4tthiUoan.tcmiosmainyitbiaeteednaabt ltehde
to provide a self-timed row
end of the burst access.
precharge
DataShee
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
A bidirectional data strobe (DQS) is transmitted externally,
patible.
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
DataSheetR4UE.Vco1m.2
Nov 10, 2005
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
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NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
256Mb DDR SDRAM
Block Diagram (64Mb x 4)
et4U.com
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
15 13
13
A0-A12,
BA0, BA1
15
2
2
11 Column-Address
Counter/Latch
Bank3
Bank1 Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
Data
(8192 x 1024 x 8)
4
Sense Amplifiers
8
4
4
DQS
1
Generator
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
COL0 Input
DQS
8 Register
Write Mask 1
8
FIFO
&
Drivers
1
2
4
8
clk
out
clk
in
Data
4
1
1
1
4
4
4
10
CK, COL0
COL0
CK
1 DataSheet4U.com
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
DataShee
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Nov 10, 2005
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
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NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
256Mb DDR SDRAM
Burst Definition
Burst Length
2
4
8
Starting Column Address
A2 A1 A0
0
1
00
01
10
11
000
001
010
011
100
101
110
111
Order of Accesses Within a Burst
Type = Sequential
0-1
Type = Interleaved
0-1
1-0 1-0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes:
et4U.com
DataSheet4U.com
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
DataShee
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet NT5DS64M4CT.PDF ] | |
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