NT5DS64M4BF Datasheet PDF - Nanya Techology
| Part Number | NT5DS64M4BF | |
| Description | (NT5DSxxMxBx) 256Mb DDR SDRAM | |
| Manufacturers | Nanya Techology | |
| Logo |  |
|
|
There is a preview and NT5DS64M4BF download ( pdf file ) link at the bottom of this page. Total 70 Pages | ||
Preview 1 page No Preview Available !
www.DataSheet4U.com
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Features
CAS Latency and Frequency
CAS
Latency
Maximum Operating Frequency (MHz)
DDR400A
(-5)
DDR400B
(-5T)
3 200
200
2.5 200
166
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• SSTL_2 compatible I/O interface
• VDDQ = 2.6V ± 0.1V
• VDD = 2.6V ± 0.1V
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
tion may be enabled to provide a self-timed row precharge
random-access memory containing 268,435,456 bits. It is
that is initiated at the end of the burst access.
internally configured as a quad-bank DRAM.
As with standard SDRAMs, the pipelined, multibank architec-
The 256Mb DDR SDRAM uses a double-data-rate architec-
ture of DDR SDRAMs allows for concurrent operation,
ture to achieve high-speed operation. The double data rate
thereby providing high effective bandwidth by hiding row pre-
architecture is essentially a 2n prefetch architecture with an
charge and activation time.
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 25D6aMtabSheet4AUn.acuotmo refresh mode is provided along with a power-saving
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
corresponding n-bit wide, one-half-clock-cycle data transfers patible.
at the I/O pins.
The functionality described and the timing specifications
A bidirectional data strobe (DQS) is transmitted externally,
included in this data sheet are for the DLL Enabled mode
along with data, for use in data capture at the receiver. DQS of operation.
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
DataSheet4U.com
DataShee
REV 1.1
04/2003
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
|
| |
 
www.DataSheet4U.com
NT5DS64M4BT NT5DS64M4BF
NT5DS32M8BT NT5DS32M8BF
NT5DS16M16BT NT5DS16M16BF
256Mb DDR SDRAM
Input/Output Functional Description
Symbol
CK, CK
CKE, CKE0, CKE1
CS, CS0, CS1
RAS, CAS , WE
DM
et4U.com
BA0, BA1
A0 - A12
DQ
DQS, LDQS, UDQS
NC
NU
VDDQ
VSSQ
VDD
VSS
VREF
Type
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Supply
Supply
Supply
Supply
Supply
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
AAudtdorPesrescIhnaprugetsDb:aiPt tfraoorSviRdheeeatedh/teW4rUroitw.ecacodomdmrmesasnfdosr,
Active commands, and the column address and
to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
DQ7; UDQS corresponds to the data on DQ8-DQ15
No Connect: No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
DQ Power Supply: 2.6V ± 0.1V.
DQ Ground
Power Supply: 2.6V ± 0.1V.
Ground
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
DataShee
DataSheet4U.com
REV 1.1
04/2003
DataSheet4 U .com
5
© NANYA TECHNOLOGY CORP. All rights reserved.
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for NT5DS64M4BF electronic component. |
| Information | Total 70 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ NT5DS64M4BF.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| NT5DS64M4BF | The function is (NT5DSxxMxBx) 256Mb DDR SDRAM. Nanya Techology | |
| NT5DS64M4BF | The function is (NT5DSxxMxBx) 256Mb DDR SDRAM. Nanya Techology | |
| NT5DS64M4BG | The function is (NT5DSxxMxBx) 256Mb DDR SDRAM. Nanya Techology | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
NT5D
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||