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PDF NT5DS64M4AT Data sheet ( Hoja de datos )
| Número de pieza | NT5DS64M4AT | |
| Descripción | (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM | |
| Fabricantes | Nanya | |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR333 (-6)
DDR300 (-66)
2 133
133
2.5 166
150
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch
CSP.
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
The DDR SDRAM provides for programmable Read or Write
random-access memory containing 268,435,456 bits. It is
burst lengths of 2, 4 or 8 locations. An Auto Precharge func-
internally configured as a quad-bank DRAM.
tion may be enabled to provide a self-timed row precharge
The 256Mb DDR SDRAM uses a double-data-rate architec-
that is initiated at the end of the burst access.
ture to achieve high-speed operation. The double data rate
As with standard SDRAMs, the pipelined, multibank architec-
architecture is essentially a 2n prefetch architecture with an
ture of DDR SDRAMs allows for concurrent operation,
interface designed to transfer two data words per clocDkactyacSleheet4thUe.rceobmy providing high effective bandwidth by hiding row pre-
at the I/O pins. A single read or write access for the 256Mb
charge and activation time.
DataShee
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Ordering Information
Part Number
NT5DS64M4AT-6
NT5DS32M8AT-6
NT5DS64M4AT-66
NT5DS32M8AT-66
NT5DS64M4AW-6
NT5DS32M8AW-6
NT5DS64M4AW-66
NT5DS32M8AW-66
Org.
x4
x8
x4
x8
x4
x8
x4
x8
CAS
Latency
2.5
2.5
2.5
2.5
Clock
(MHz)
166
150
166
150
CAS
Latency
2
2
2
2
Clock
(MHz)
133
133
133
133
Speed
DDR333
DDR300
Package
66 pin TSOP-II
DDR333
DDR300
60 balls CSP
et4U.com
DataSheet4U.com
DataShee
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© NANYA TECHNOLOGY CORP. All rights reserved.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.
Truth Table 1a: Commands
Name (Function)
Deselect (Nop)
No Operation (Nop)
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
CS RAS CAS WE
HXXX
L HHH
L LHH
LHLH
LHL L
L HHL
L LHL
L L LH
LLLL
Address
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
MNE
NOP
NOP
ACT
Read
Write
BST
PRE
AR / SR
MRS
Notes
1, 9
1, 9
1, 3
1, 4
1, 4
1, 8
1, 5
1, 6, 7
1, 2
et4U.com
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-
charge feature (nonpersistent), A10 low disables the ADutaotParSechheaergte4Ufea.ctuorme.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
DataShee
Truth Table 1b: DM Operation
Name (Function)
Write Enable
Write Inhibit
1. Used to mask write data; provided coincident with the corresponding data.
DM
DQs
Notes
L Valid 1
HX 1
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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