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PDF W78E65 Data sheet ( Hoja de datos )

Número de pieza W78E65
Descripción 8-Bit Microcontroller
Fabricantes Winbond 
Logotipo Winbond Logotipo



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W78E65 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................ 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION ................................................................................................... 6
6.1 RAM ................................................................................................................................ 6
6.2 Timers 0, 1, and 2........................................................................................................... 7
6.2.1 Timer 2 Output .................................................................................................................7
6.3 Clock ............................................................................................................................... 8
6.3.1 Crystal Oscillator ..............................................................................................................8
6.3.2 External Clock ..................................................................................................................8
6.4 Power Management........................................................................................................ 8
6.4.1 Idle Mode..........................................................................................................................8
6.4.2 Power-down Mode.....D...a..t.a..S...h..e..e..t..4..U.....c..o..m..........................................................................8
6.4.3 Reduce EMI Emission ......................................................................................................8
6.5 Reset............................................................................................................................... 9
6.5.1 W78E65 Special Function Registers (SFRs) and Reset Values.......................................9
6.6 Port 4 ............................................................................................................................ 10
6.6.1 Port Options Register .....................................................................................................10
6.6.2 INT2 / INT3 ...................................................................................................................10
6.6.3 Port 4 Base Address Registers.......................................................................................12
6.7 Pulse Width Modulated Outputs (PWM)....................................................................... 14
6.8 Watchdog Timer ........................................................................................................... 17
6.9 In-System Programming (ISP) Mode............................................................................ 19
6.9.1 In-System Programming Control Register (CHPCON) ...................................................20
6.10 Software Reset ............................................................................................................. 21
6.11 H/W Reboot Mode (Boot from LD FLASH EPROM) .................................................... 21
6.12 Security ......................................................................................................................... 24
7. ELETRICAL CHARACTERISTICS ........................................................................................... 25
7.1 Absolute Maximum Ratings .......................................................................................... 25
7.2 DC Characteristics........................................................................................................ 25
7.3 AC Characteristics ........................................................................................................ 27
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Publication Release Date: August 25, 2005
- 1 - Revision A6
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4. PIN DESCRIPTION
SYMBOL
EA
TYPE
I
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0P0.7
P1.0P1.7
P2.0P2.7
P3.0P3.7
P4.0P4.3
OH
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
IL
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: ground potential.
I
I/O D
POWER SUPPLY:DSautapSphlyeveot4ltUag.ceofmor operation.
PORT 0: Function is the same as that of standard 8052. This port also
provides a multiplexed low order address/data bus during accesses to
external memory. Port 0 has internal pull-up resisters enabled by software.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
and P2.7 also provide the alternate function REBOOT which is H/W reboot
from LD flash.
I/O H PORT 3: Function is the same as that of the standard 8052.
PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function
I/O H
REBOOT which is H/W reboot from LD flash.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt information:
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
2BH
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6
7 (lowest)
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ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.2
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
-
XICON.0
XICON.3
P4CONB (C3H)
BIT NAME
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1 and
P43CMP0.
7, 6 P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The
P43FUN0 address range depends on the SFR P43AH, P43AL, P43CMP1 and
P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
5, 4
P43CMP1
01: Compare the 15 high bits (A15A1) of address bus with the base address
register P43AH, P43AL.
P43CMP0
10: Compare the 14 high bits (A15A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15A8) of address bus with the base address
register P43AH, P43AL.
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Publication Release Date: August 25, 2005
Revision A6
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