PDF M53230224CE2 Data sheet ( Hoja de datos )

Número de pieza	M53230224CE2
Descripción	(M53230224CE2/CJ2) DRAM Module
Fabricantes	Samsung Semiconductor
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No Preview Available ! www.DataSheet4U.com DRAM MODULE M53230224CE2/CJ2 M53230224CE2/CJ2 Extended Data Out 2M x 32 DRAM SIMM using 1Mx16 , 1K Refresh, 5V GENERAL DESCRIPTION The Samsung M53230224D is a 2Mx32bits Dynamic RAM high density memory module. The Samsung M53230224D consists of four CMOS 1Mx16bits DRAMs in 42-pin SOJ pack- age mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M53230224D is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC -50 50ns 15ns 90ns 25ns -60 60ns 15ns 110ns 30ns FEATURES • Part Identification - M53230224CE2-C(1024 cycles/16ms Ref, SOJ, Solder) - M53230224CJ2-C(1024 cycles/16ms Ref, SOJ, Gold) • Extended Data Out • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • TTL compatible inputs and outputs • Single +5V±10% power supply • JEDEC standard PDPin & pinout • PCB : Height(750mil), double sided component PIN CONFIGURATIONS Pin Symbol Pin Symbol 1 VSS 37 NC 2 DQ0 38 NC 3 DQ16 39 Vss 4 DQ1 40 CAS0 5 DQ17 41 CAS2 6 DQ2 42 CAS3 7 DQ18 43 CAS1 8 DQ3 44 RAS0 9 DQ19 45 RAS1 10 Vcc 46 NC 11 NC 47 W 12 A0 48 NC 13 A1 49 DQ8 14 A2 50 DQ24 15 A3 51 DQ9 16 A4 52 DQ25 17 A5 53 DQ10 18 A6 54 DQ26 19 NC 55 DQ11 20 DQ4 56 DQ27 21 DQ20 57 DQ12 22 DQ5 58 DQ28 23 DQ21 59 Vcc 24 DQ6 60 DQ29 25 DQ22 61 DQ13 26 DQ7 62 DQ30 27 DQ23 63 DQ14 28 A7 64 DQ31 29 NC 65 DQ15 30 Vcc 66 NC 31 A8 67 PD1 32 A9 68 PD2 33 RAS1 69 PD3 34 RAS0 70 PD4 35 NC 71 NC 36 NC 72 Vss PIN NAMES Pin Name A0 - A9 DQ0 - DQ31 DataSheet4U.com W RAS0 , RAS1 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Res Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection Reserved Pin PRESENCE DETECT PINS (Optional) Pin 50NS 60NS PD1 NC PD2 NC PD3 Vss PD4 Vss NC NC NC NC * Pin connection changing available DataShee SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. DataSheet4U.com - 1 - Rev. 0.0 (Oct. 1999) DataSheet4 U .com 1 page www.DataSheet4U.com DRAM MODULE M53230224CE2/CJ2 AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Hyper page mode cycle time CAS precharge time(Hyper page cycle) RAS pulse width(Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width (Hyper Page Cycle) Symbol tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE -50 Min Max 25 8 50 200K 30 10 10 5 3 13 3 13 15 5 -60 Min Max 30 10 60 200K 35 10 10 5 3 15 3 15 15 5 Unit Note ns 13 ns ns ns ns ns ns ns 6,11,12 ns 6,11 ns ns NOTES 1. An initial pause of 200us is required after power-up followed 8. Either tRCH or tRRH must be satisfied for a read cycle. by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 9. These parameter are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write et4U.com2. VIH(min) and VIL(max) are reference levels for mDeaatsauSrihneget4U.ccoymcles. timing of input signals. Transition times are measured DataShee between VIH(min) and VIL(max) and are assumed to be 5ns 10. Operation within the tRAD(max) limit insures that tRAC(max) for all inputs. can be met. tRAD(max) is specified as reference point only. If 3. Measured with a load equivalent to 2 TTL loads and 100pF. tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 12. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condi- tion of the output is achieved by RAS high going. 13. tASC≥tCP min 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. DataSheet4U.com DataSheet4 U .com - 5 - Rev. 0.0 (Oct. 1999) 5 Page www.DataSheet4U.com DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) M53230224CE2/CJ2 VIH - RAS VIL - VIH - CAS VIL - VIH - A VIL - VIH - W VIL - et4U.com VOH - DQ VOL - tRC tRAS tRP tRC tRAS tCRP tRCD tRSH tASR tRAD tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS tRRH tCHR tWRH tWRP tRP tAA tCAC DattCaLSZheet4U.com tRAC OPEN tREZ tWEZ DATA-OUT tCEZ DataShee Don′t care Undefined DataSheet4U.com DataSheet4 U .com - 11 - Rev. 0.0 (Oct. 1999) 11 Page

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