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PDF ADSST-SALEM-3T Data sheet ( Hoja de datos )
| Número de pieza | ADSST-SALEM-3T | |
| Descripción | Powerful Energy Meter Chipset | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Powerful Energy Meter Chipset
ADSST-SALEM-3T
FEATURES
High accuracy
Supports IEC 60687/61036 and ANSI C12.1/12.20
Suitable for class0.5 and class0.2 meter
Full four quadrant measurement of parameters
SPI® compatible serial interface
Pulse output with programmable pulse constant as
pulses/kWh or Wh/pulse
Programmable duty cycle for pulse output
chipset can be interfaced to any general-purpose microproces-
sor to develop state of the art tri-vector or polyphase energy
metering solutions with a wide range of basic currents from 1 A
to 30 A. By incorporating a comprehensive data set of parame-
ters, including instantaneous measurements, accumulated
parameters, and harmonic analysis data, the ADSST-SALEM-3T
chipset meets high end energy metering requirements. The abil-
ity to easily configure the chipset for various parameters makes
it a very flexible solution.
Embedded calibration routines for gain and dc offset
The phase and nonlinearity compensation for current
Software based phase and nonlinearity compensation for
current transformers
15 kHz sampling frequency
UART mode enables a PC to directly access all computed
parameters
Flags to indicate tamper conditions
Single 3.0 V supply
transformers is done in software (patent pending) without
having to use any passive components in the circuit for
compensation, thus minimizing variations in accuracy with
temperature and time.
The ADSST-SALEM-3T measures and computes a large num-
ber of parameters essential for high end metering.
Developer’s kit to accelerate design process (See
Table 1.
Ordering Guide for separate ordering number.)
Parameter
GENERAL DESCRIPTION
DataSheet4U.cRoMmS Voltage
The ADSST-SALEM-3T energy meter chipset consists of an
efficient ADSST-218x digital signal processor (DSP), a fast and
accurate 6-channel, 16-bit ADSST-73360LAR sigma-delta ana-
log-to-digital converter (ADC), and metering software. Two
chipset versions are available to support differing ranges of
operating temperature: The ADSST-EM-3040 chipset is rated at
0°C to 70°C for commercial applications, while the ADSST-EM-
RMS Current
Active Power
Apparent Power
Inductive Reactive Power
Capacitive Reactive Power
Power Factor
Frequency
3041 chipset operates at –25°C to +85°C for industrial use.
Positive Active Energy
Negative Active Energy
Each Phase TotalDataShee
SMPS
RESISTOR
BLOCK
CT
DSP
ADC
LCD DISPLAY
SPI BUS
BOOT
FLASH
µC
Apparent Energy
Positive Inductive Reactive Energy
Negative Inductive Reactive Energy
Positive Capacitive Reactive Energy
Negative Capacitive Reactive Energy
CT
FLASH
CT ADSST-EM-3040
OPTO
Voltage Magnitude and Phase for All
Odd Harmonics up to 21st Order
RTC
RS-232
03738-0-001
Current Magnitude and Phase for All
Odd Harmonics up to 21st Order
Figure 1. Block Diagram of a Functional Meter
The ADC and DSP are interfaced to simultaneously acquire
voltage and current samples on all three phases and to perform
mathematically intensive computations to calculate various
instantaneous parameters and perform harmonic analysis. The
The ADSST-SALEM-3T offers some excellent features that
make the final meter cost-effective and easy to manufacture.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
DataSheet4Uinf.rcinogemments of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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ADSST-SALEM-3T
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus Program Memory
Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG0). One execution mode (go mode) enables the
ADSST-218x to continue running from on-chip memory. Nor-
mal execution mode requires the processor to halt while buses
are granted.
The ADSST-218x can respond to 11 interrupts. There are up to
six external interrupts (one edge sensitive, two level sensitive,
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the byte DMA port, and
the power-down circuitry. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation.
Serial Ports
The ADSST-218x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Package Description
The ADSST-218x is available in a 100-lead low profile quad flat
package (LQFP, refer to Figure 5).
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ADSST-SALEM-3T
GENERAL DESCRIPTION OF THE ADSST-73360LAR
ADC
The ADSST-73360LAR is a 6-channel input analog front end
processor for general-purpose applications, including industrial
power metering or multichannel analog inputs. It features six
16-bit A/D conversion channels, each of which provides 76 dB
signal-to-noise ratio over a dc to 4 kHz signal bandwidth. Each
channel also features an input programmable gain amplifier
(PGA) with gain settings in eight stages from 0 dB to 38 dB.
The ADSST-73360LAR is particularly suitable for industrial
power metering as each channel samples synchronously, ensur-
ing that there is no (phase) delay between the conversions. The
ADSST-73360LAR also features low group delay conversions on
all channels.
An on-chip reference voltage is included with a nominal value
of 1.2 V.
The ADSST-73360LAR is available in a 28-lead SOIC package.
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VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
REFCAP
REFOUT
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
SIGNAL
CONDITIONING
0/38DB
PGA
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
SIGNAL
CONDITIONING
0/38DB
PGA
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
SIGNAL
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
REFERENCE
ADSST-73360LAR
0/38DB
PGA
DataSheet4U.com
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
SIGNAL
CONDITIONING
0/38DB
PGA
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
SIGNAL
CONDITIONING
0/38DB
PGA
SIGNAL
Σ-∆
CONDITIONING
DECIMATOR
Figure 6. ADSST-73360LAR Functional Block Diagram
SDI
SDIFS
SCLK
SERIAL
I/O
PORT
RESET
MCLK
SE
SDO
SDOFS
03738-0-004
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