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PDF TC74ACT164FN Data sheet ( Hoja de datos )
| Número de pieza | TC74ACT164FN | |
| Descripción | 8 BIT SHIFT REGISTER | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC74ACT164P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT164P,TC74ACT164F,TC74ACT164FN,TC74ACT164FT
8-Bit Shift Register (S-IN, P-OUT)
The TC74ACT164 is an advanced high speed CMOS 8-BIT
SERIAL-IN PARALLEL-OUT SHIFT REGISTER fabricated with
silicon gate and double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
It consists of a serial-in, parallel-out 8-bit shift register with a
CLOCK input and an overriding CLEAR input.
Two serial data inputs (A, B) are provided so that one may be
used as a data enable.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: The JEDEC SOP (FN) is not available in
Japan.
TC74ACT164P
TC74ACT164F
Features
• High speed: fmax = 200 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 8 µA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (max)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
tansmission lines.
• Balanced propagation delays: tpLH ≈ tpHL
• Pin and function compatible with 74F164
TC74ACT164FN
TC74ACT164FT
Weight
DIP14-P-300-2.54: 0.96 g (typ.)
SOP14-P-300-1.27: 0.18 g (typ.)
SOL14-P-150-1.27: 0.12 g (typ.)
TSSOP14-P-0044-0.65: 0.06 (typ.)
1 2003-06-23
1 page  
Timing Requirements (input: tr = tf = 3 ns)
Characteristics
Minimum pulse width (CK)
Minimum pulse width
( CLR )
Minimum set-up time
Minimum hold time
Minimum removal time
( CLR )
Symbol
tW (L)
tW (H)
tW (L)
ts
th
trem
Test Condition
TC74ACT164P/F/FN/FT
VCC (V)
Ta = 25°C
Ta = −40~85°C
Unit
Typ. Limit
Limit
5.0 ± 0.5
5.0
5.0
5.0 ± 0.5
5.0
5.0
5.0 ± 0.5
3.0
3.0
ns
5.0 ± 0.5
2.6
2.6
5.0 ± 0.5
2.0
2.0
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Characteristics
Propagation delay time
(CK-Q)
Propagation delay time
( CLR -Q)
Maximum clock frequency
Input capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpHL
fmax
CIN
CPD
(Note 3)
Test Condition
VCC (V)
Ta = 25°C
Ta = −40~85°C
Min Typ. Max Min Max
Unit
5.0 ± 0.5 6.6 11.0 1.0 12.5
5.0 ± 0.5 6.9 11.0 1.0 12.5
ns
5.0 ± 0.5 80 150
5 10
101
80
MHz
10
pF
Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD ⋅ VCC ⋅ fIN + ICC
5 2003-06-23
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC74ACT164FN.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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| TC74ACT164FN | 8 BIT SHIFT REGISTER | Toshiba Semiconductor |
| TC74ACT164FT | 8 BIT SHIFT REGISTER | Toshiba Semiconductor |
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