DataSheetWiki


PEX8114 fiches techniques PDF

PLX Technology - PCI Express to PCI Bridge

Numéro de référence PEX8114
Description PCI Express to PCI Bridge
Fabricant PLX Technology 
Logo PLX Technology 





1 Page

No Preview Available !





PEX8114 fiche technique
www.DataSheet4U.com
. Version 2.1 2004
PEX 8114
Features
ƒ General Features
o Forward and Reverse bridging
o Reverse bridging root functions
o Transparent and Non-transparent
bridging
o Standard 256 Plastic BGA package
(17mm x 17mm)
o Low power – 2W max.
o No heat sink required
o EEPROM configuration option
o 1.0 V core supply voltage
o DC and AC JTAG (1149.1 and
1149.6)
ƒ Scalable PCI Express Interface
o x4 Link (configurable as x1, x2 or x4)
o Full-duplex PCI Express lanes;
2.5 Gbps each
o Automatic lane reversal
o 8b/10b encoding
o Link training (auto-negotiate to
smallest link width)
o 256 byte maximum payload size
o PCI Express Base specification 1.0a
compliant
o End-to-end CRC and data poisoning
o Advanced error reporting
o Link and device power management
o Advanced flow control
o Hot Plug
o Turn off unused lanes for power
reduction
ƒ Advanced PCI-X Interface
o PCI-X (v 1.0b): 64 bits at 133, 100 or
66 MHz
o PCI 3.0: 32 or 64 bits at 66, 50, 33 or
25 MHz
o 8-outstanding split transactions
o Internal arbiter supports up to 4
external masters
o 3.3V I/O
o Message Signal Interrupt (MSI)
support
o Provides up to four PCI/PCI-X clocks
o Scratchpad and doorbell registers
DataSheet4U.com
DataSheet4 U .com
ExpressLane™ PCI Express-to-PCI/PCI-X Bridge
Flexible, High-Performance Bridge in a Small Package
The PLX Technology ExpressLane PEX 8114 is a high performance bridge that
enables designers to migrate legacy PCI and PCI-X bus interfaces to the new
advanced serial PCI Express™ interface. This flexible device supports forward,
reverse and non-transparent bridging.
The bridge is equipped with a standard, but flexible PCI Express port that scales to
x1, x2 or x4 lanes with a maximum of 1 Gigabyte per second of throughput per
transmit and receive direction. With four 2.5 Gbps integrated SerDes, the standard
PCI Express signaling delivers the highest bandwidth with the lowest possible pin
count using LVDS technology.
The ExpressLane PEX 8114 has a single parallel bus segment supporting the
advanced PCI-X protocol, with a 64-bit wide parallel data path running at 133MHz.
The bridge also supports conventional PCI operation.
While both sides of the bridge are evenly matched, the device also supports internal
queues with flow control features to optimize throughput and traffic flow.
DataShee
The smaDlla1ta7mShmexet147Um.cmomfootprint in standard Plastic BGA packaging makes the
ExpressLane PEX 8114 ideal for a variety of applications where board real estate is
at a premium.
Forward and Reverse Bridging
Compliant to the PCI Express-to-PCI/PCI-X Bridge Specification 1.0, the
ExpressLane PEX 8114 is capable of operating in either forward or reverse bridging
modes. In forward mode, the bridge allows legacy PCI or PCI-X chips and adapters
to be used with new PCI Express processor systems. Reverse bridge operation allows
conventional PCI or PCI-X processors and chipsets to configure and control
advanced PCI Express switches and endpoints. The reverse bridge not only allows
complete configuration of a downstream PCI Express system from the PCI/PCI-X
bus, but it also handles limited PCI Express root functions for reverse interrupt and
advanced error handling.
Non-Transparent Bridging
The ExpressLane PEX 8114 can be configured as a non-transparent bridge when
operating in forward mode. Non-transparent bridging is used to design intelligent I/O
and storage adapters as well as to enable multi-host systems. The non-transparency
features are implemented in the same fashion as conventional PCI-to-PCI bridge
applications.
Non-Transparent bridges allow systems to isolate CPU and memory spaces to
connect two independent address/processor domains. The bridge includes doorbell
registers to send interrupts from each side to the other and scratchpad registers
accessible from both sides for inter-processor communications.
High Performance PCI Express Interface
The fully integrated PCI Express interface incorporates many of the advanced
protocol features in PCI Express such as Automatic Lane Reversal, ECRC, Data
Poisoning, Link State Power Management and Hot Plug. The single link scales from
x4 to x2 or x1 operation through configuration or automatic link training. This
enables the user to reduce power consumption by turning off unused lanes.
DataSheet4U.com

PagesPages 4
Télécharger [ PEX8114 ]


Fiche technique recommandé

No Description détaillée Fabricant
PEX8111 PCI Express to PCI Bridge PLX Technology
PLX Technology
PEX8111 PEX8111 / PEX8114 ETC
ETC
PEX8111 Rapid Development Kit Paltek
Paltek
PEX8114 PCI Express to PCI Bridge PLX Technology
PLX Technology

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche