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PDF HM628128ALP Data sheet ( Hoja de datos )
| Número de pieza | HM628128ALP | |
| Descripción | High Speed CMOS Static RAM | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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ADE-XXX-XXX
HM628128A Series
131,072-word × 8-bit High Speed CMOS Static RAM
Rev. X
January 1995
The Hitachi HM628128A is a CMOS static RAM Features
organized 128 kword × 8 bit. It realizes higher
density, higher performance and low power • High speed
consumption by employing 0.8 µm Hi-CMOS
— Fast access time: 55/70/85/100 ns (max)
process technology.
• Low power
It offers low power standby power dissipation;
— Active: 75 mW (typ)
therefore, it is suitable for battery back-up systems.
— Standby: 10 µW (typ)
The device, packaged in a 525-mil SOP (460-mil
body SOP) or a 600-mil plastic DIP, or a 8 × 20
mm TSOP with thickness of 1.2 mm, is available
for high density mounting. TSOP package is
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
suitable for cards, and reverse type TSOP is also
provided.
• Equal access and cycle times
DataSheet4•UC.coommmon data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
2 chip selection for battery back up
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Absolute Maximum Ratings
Parameter
Symbol
Supply voltage relative to VSS
Voltage on any pin relative to VSS*1
Power dissipation
Operating temperature
VCC
VT
PT
Topr
Storage temperature
Tstg
Storage temperature under bias
Tbias
Note: 1. With respect to VSS
2. –3.0 V for pulse half-width ≤ 30 ns
3. Maximum voltage is 7.0V.
HM628128A Series
Value
–0.5 to +7.0
–0.5 *2 to VCC + 0.3*3
1.0
0 to +70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Supply voltage
VCC 4.5
5.0
et4U.com Input voltage
VSS 0
VIH 2.2
0
—
(HM628128A-7/8/10)
VIL
–0.3 *1
—
Input voltage
VIH DataS2h.4eet4U.com —
(HM628128A-5)
VIL
–0.3 *1
—
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
Max
5.5
0
VCC + 0.3
0.8
VCC + 0.3
0.8
Unit
V
V
V
V
V
V
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Write Timing Waveform (2) (OE low Fixed)
t WC
Address
Address Valid
t CW *2
CS1
*6
HM628128A Series
t
*4
WR
CS2
WE
et4U.com
Dout
Din
t AS *3
t AW
t WP *1 *11
t WHZ *5
t OW
High Impedance
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t DW
t DH
Data Valid
t OH
*7
*9
DataShee
*8
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the
latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the
earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS1 goes low simultaneously with WE going low or after the WE going low, the outputs
remain in a high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of next address.
9. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of opposite phase to the outputs must not be applied to them.
10. This parameter is sampled and not 100% tested.
DataSheet4U.co1m1. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HM628128ALP.PDF ] | |
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