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PDF NST3946DXV6T5 Data sheet ( Hoja de datos )

Número de pieza NST3946DXV6T5
Descripción (NST3946DXV6T1 / NST3946DXV6T5) Dual General Purpose Transistor
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NST3946DXV6T1,
NST3946DXV6T5
Dual General Purpose
Transistor
The NST3946DXV6T1 device is a spin- off of our popular
SOT-23/SOT-323 three-leaded device. It is designed for general
purpose amplifier applications and is housed in the SOT- 563
six-leaded surface mount package. By putting two discrete devices in
one package, this device is ideal for low-power surface mount
applications where board space is at a premium.
hFE, 100-300
Low VCE(sat), 0.4 V
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Lead-Free Solder Plating
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(3) (2) (1)
Q1 Q2
(4) (5)
(6)
NST3946DXV6T1*
*Q1 PNP
Q2 NPN
MAXIMUM RATINGS
Rating
Collector - Emitter Voltage
(NPN)
(PNP)
Collector - Base Voltage
(NPN)
(PNP)
Symbol
VCEO
VCBO
Value
Unit
Vdc
40
D-4a0taSheet4U.com
Vdc
60
-40
Emitter - Base Voltage
(NPN)
(PNP)
VEBO
6.0
-5.0
Vdc
Collector Current - Continuous
(NPN)
(PNP)
IC mAdc
200
-200
Electrostatic Discharge
ESD
HBM>16000,
MM>2000
V
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
Total Device Dissipation
Derate above 25°C
TA = 25°C
PD
357
(Note 1)
2.9
(Note 1)
mW
mW/°C
Thermal Resistance
Junction-to-Ambient
RqJA
350
(Note 1)
°C/W
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
Total Device Dissipation
Derate above 25°C
TA = 25°C
PD
500
(Note 1)
4.0
(Note 1)
mW
mW/°C
1. FR-4 @ Minimum Pad
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654
12 3
SOT-563
CASE 463A
PLASTIC
MARKING DIAGRAM
46 D
46 = Specific Device Code
D = Date Code
ORDERING INFORMATION
Device
Package
Shipping
NST3946DXV6T1 SOT-563
4 mm pitch
4000/Tape & Reel
NST3946DXV6T5 SOT-563
2 mm pitch
8000/Tape & Reel
© Semiconductor Components Industries, LLC, 2003
March, 2003 - Rev. 0
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1 Publication Order Number:
NST3946DXV6T1/D
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NST3946DXV6T1, NST3946DXV6T5
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(NPN)
500 500
300
IC/IB = 10
300
VCC = 40 V
200 200 IC/IB = 10
100
70 tr @ VCC = 3.0 V
50
30
20
40 V
10 (NPN)
7
5
1.0 2.0 3.0
15 V
td @ VOB = 0 V
2.0 V
5.0 7.0 10
20 30 50 70 100
200
IC, COLLECTOR CURRENT (mA)
Figure 4. Turn - On Time
500
300
200 IC/IB = 20
IC/IB = 10
ts = ts 1/8 tf
IB1 = IB2
100
70
50 IC/IB = 20
30 IC/IB = 10
20
100
70
50
30
20
10 (NPN)
7
5
1.0 2.0 3.0
5.0 7.0 10
20 30 50 70 100
IC, COLLECTOR CURRENT (mA)
Figure 5. Rise Time
200
500
300 VCC = 40 V
200 IB1 = IB2
IC/IB = 20
100
70
50
30 IC/IB = 10
20
10 (NPN)
7
5
1.0 2.0 3.0
5.0 7.0 10
20 30
DataSheet4U1.c0 om(NPN)
7
50 70 100 200
5
1.0 2.0 3.0
5.0 7.0 10
20 30 50 70 100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 6. Storage Time
Figure 7. Fall Time
200
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TYPICAL AUDIO SMALL- SIGNAL CHARACTERISTICS
NOISE FIGURE VARIATIONS
(VCE = 5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz)
12
SOURCE RESISTANCE = 200 W
10 IC = 1.0 mA
8 SOURCE RESISTANCE = 200 W
IC = 0.5 mA
6 SOURCE RESISTANCE = 1.0 k
IC = 50 mA
4
2 SOURCE RESISTANCE = 500 W
IC = 100 mA
0
0.1 0.2 0.4
1.0 2.0 4.0
(NPN)
10 20
f, FREQUENCY (kHz)
40
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Figure 8. Noise Figure
100
14
12 f = 1.0 kHz IC = 1.0 mA
10 IC = 0.5 mA
8
6
IC = 50 mA
IC = 100 mA
4
2
0
0.1 0.2
(NPN
)
0.4 1.0 2.0 4.0 10 20
RS, SOURCE RESISTANCE (k OHMS)
Figure 9. Noise Figure
40
100
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NST3946DXV6T5 arduino
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NST3946DXV6T1, NST3946DXV6T5
INFORMATION FOR USING THE SOT-563 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.3
0.45
1.0
1.35
0.5 0.5
Dimensions in mm
SOT-563
SOT-563 POWER DISSIPATION
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The power dissipation of the SOT-563 is a function of
the pad size. This can vary from the minimum pad size for
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the
soldering to a pad size
tion. Power dissipation
given for maximum
for a surface mount
power
device
idsDisdaseittpaeaSr--heet4Urhae.tcaetodemdtetmo paehraigtuhrteeomfptehreatduervei,cfea.ilWurheetno
the entire
complete
device is
soldering
mined by TJ(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
SOT-563 package, PD can be calculated as follows:
Always preheat the device.
PD =
TJ(max) - TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 150 milliwatts.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
PD =
150°C - 25°C
833°C/W
= 150 milliwatts
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
The 833°C/W for the SOT-563 package assumes the use
After soldering has been completed, the device should
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 150 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT-563 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad®. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device
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