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PDF KS0086 Data sheet ( Hoja de datos )
| Número de pieza | KS0086 | |
| Descripción | 80Ch Common . Segment Driver | |
| Fabricantes | Samsung Electronics | |
| Logotipo |  |
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KS0086
80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD
INTRODUCTION
The KS0086 is an LCD driver LSI which is fabricated by low power
CMOS high voltage process technology.
In segment driver mode, it can be interfaced in 1-bit serial or 4-bit
parallel method by the controller.
In common driver mode, dual type mode is applicable. And in seg-
ment mode application, the power down function reduces power
consumption.
100 QFP-1420C
FEATURES
• Power supply voltage : +5 V ± 10 %, + 3 V ± 10 %
• Supply voltage for display : 6 to 28 V (VDD-VEE)
• 4-bit parallel/1-bit serial data processing (in segment mode).
• Single mode operation / dual mode operation (in common
mode).
• Power down function (in segment mode).
• Applicable LCD duty : 1/64 ~ 1/256
• Interface
100 TQFP-1414
DRIVER
COM (cascade)
KS0086
SEG (cascade)
DataSheet4U.com
KS0086
• High voltage CMOS process
• Available PKG type : bare chip, 100-QFP, 100-TQFP and 100-TAB.
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KS0086
80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD
PAD LOCATION (KS0086/KS0086TB)
PAD
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PAD
NAME
SC51
SC52
SC53
SC54
SC55
SC56
SC57
SC58
SC59
SC60
SC61
SC62
SC63
SC64
SC65
SC66
SC67
SC68
SC69
SC70
SC71
SC72
SC73
SC74
SC75
SC76
SC77
SC78
SC79
SC80
ERB
VEE
V5
V43
COORDINATES
XY
-1690 1959
-2029 1884
-2029 1750
-2029 1616
-2029 1482
-2029 1348
-2029 1214
-2029 1080
-2029
946
-2029
812
-2029
678
-2029
544
-2029
410
-2029
276
-2029
142
-2029
8
-2029
-126
-2029
-260
-2029
-394
-2029
-528
-2029
-662
-2029
-797
-2029
-931
-2029 -1065
-2029 -1199
-2029 -1333
-2029 -1467
-2029 -1601
-2029 -1735
-2029 -1884
-1479 -1959
-1275 -1959
-1150 -1959
-1025 -1959
PAD
NO.
PAD
NAME
COORDINATES
XY
35
V12
-900
-1959
36
V0
-775
-1959
37
CS
-600
-1959
38
M
-475
-1959
39
DISPOFFB
-350
-1959
40
VDD
-225
-1959
41
SHL
-100
-1959
42
VSS
25 -1959
43
D4_DR
266 -1959
44
D3_DM
470 -1959
45
D2_DL
711 -1959
46
D1_SID
915 -1959
47
CL2
1040
-1959
48
ELB
1165
-1959
49
CL1
1290
-1959
50
ELB
1496
-1959
51 DataSSCh1eet4U2.0c2o9m -1884
52
SC2
2029
-1735
53
SC3
2029
-1601
54
SC4
2029
-1467
55
SC5
2029
-1333
56
SC6
2029
-1199
57
SC7
2029
-1065
58
SC8
2029
-931
59
SC9
2029
-797
60
SC10
2029
-662
61
SC11
2029
-528
62
SC12
2029
-394
63
SC13
2029
-260
64
SC14
2029
-126
65
SC15
2029
8
66
SC16
2029
142
67
SC17
2029
276
68
SC18
2029
410
PAD
NO.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PAD
NAME
SC19
SC20
SC21
SC22
SC23
SC24
SC25
SC26
SC27
SC28
SC29
SC30
SC31
SC32
SC33
SC34
SC35
SC36
SC37
SC38
SC39
SC40
SC41
SC42
SC43
SC44
SC45
SC46
SC47
SC48
SC49
SC50
COORDINATES
XY
2029
544
2029
678
2029
812
2029
946
2029
1080
2029
1214
2029
1348
2029
1482
2029
1616
2029
1750
2029
1884
1690
1959
1529
1959
1368
1959
1207
1959
1046
1959
885 1959
724 1959
563 1959
402 1959
241 1959
80 1959
-80 1959
-241
1959
-402
1959
-563
1959
-724
1959
-885
1959
-1046
1959
-1207
1959
-1368
1959
-1529
1959
5
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KS0086
80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
Pin
Input
Output
VDD
VSS
VEE
V0, V12,
V43, V5
Input
SC1
~
SC80
Output
CL2 Input
M Input
CL1 Input
DISPOFFB Input
CS Input
Name
Function
Interface
Power
supply
LCD driver
output
voltage level
LCD driver
output
Data shift
clock
AC signal
for LCD
driver output
Data latch
clock
Display off
control
COM/SEG
mode
control
Logical "High" input port (+5 V ± 10%, +3 V ± 10%)
0 V (GND)
Logical "Low" for high voltage part
Bias supply voltage input to drive the LCD.
Bias voltage divided by the resistance is usually used as a supply
voltage source (refer to NOTE 2).
Display data output pin which corresponds to the respective latch
contents.
One of V0, V12, V34 and V5 is selected as a display driving volt-
age source according to the combination of the latched data level
and M signal (refer to NOTE 1).
Clock pulse input for the bi-directional shift register.
- In segment driver application mode, the data is shifted to 20 x 4-
bit segment data shift register at the falling edge of this clock pulse.
The clock pulse, which was input when the enable bit (ELB/ERB)
is in not active condition, is invalid.
- In common driver application mode, the data is shifted to 80-bit
common data bi-directional shift register by the
CL1 clock. Hence, this clock pin is not used (Open or connect this
pin to VDD).
Alternate signal input pin for LCD driving.
NormDal afratamSe hineveerst4ioUn s.icgonaml is input in to this pin.
- In segment driver application mode, this signal is used for latch-
ing the shift register contents at the falling edge of this clock pulse.
CL1 pulse "High" level initializes power-down function block.
- In common driver application mode, CL1 is used as a shifting
clock of common output data.
Control input pin to fix the driver output (SC1~SC80) to V0 level,
during "Low" value input. LCD becomes non-selected by V0 level
output from every output of segment drivers and every output of
common drivers.
When CS = "Low", KS0086 is used as an 80-bit segment driver.
When CS = "High", KS0086 is set to an 80-bit common driver
According to the input value of the AMS and the CS pin, applica-
tion mode of KS0086 is differs as shown below.
Power
Power
LCD
Controller
Controller
Controller
Controller
VDD/VSS
AMS
Input
Application
mode select
CS AMS
00
01
10
11
Application mode
4-bit parallel interface mode
1-bit serial interface mode
single-type application mode
dual-type application mode
COM/SEG
SEG
COM
VDD/VSS
11
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KS0086.PDF ] | |
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