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PDF 54HCT273 Data sheet ( Hoja de datos )
| Número de pieza | 54HCT273 | |
| Descripción | CD54HCT273 | |
| Fabricantes | ETC | |
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Data sheet acquired from Harris Semiconductor
SCHS174
February 1998
CD74HC273,
CD74HCT273
High Speed CMOS Logic
Octal D-Type Flip-Flop with Reset
[ /Title
(CD74
HC273
,
CD74
HCT27
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Octal
D-
Type
Flip-
Features
Description
• Common Clock and Asynchronous Master Reset
• Positive Edge Triggering
• Buffered Inputs
• TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The Harris CD74HC273 and CD74HCT273 high speed octal
D-Type flip-flops with a direct clear input are manufactured
with silicon-gate CMOS technology. They possess the low
power consumption of standard CMOS integrated circuits.
Information at the D inputis transferred to the Q outputs on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All eight Q outputs are reset to a
logic 0.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
PKG.
NO.
CD54HC273F
-55 to 125 20 Ld CERDIP F20.3
CD54HCT273F
-55 to 125 20 Ld CERDIP F20.3
CD74HC273E
-55 to 125 20 Ld PDIP
E20.3
CD74HCT273E
-55 to 125 20 Ld PDIP
E20.3
CD74HC273M
-55 to 125 20 Ld SOIC
M20.3
CD74HCT273M
-55 to 125 20 Ld SOIC
M20.3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD54HC273, CD54HCT273, CD74HC273, CD74HCT273
(PDIP, SOIC, CERDIP)
TOP VIEW
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 1479.2
1 page  
CD74HC273, CD74HCT273
Prerequisite For Switching Specifications (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Clock Pulse Width (Figure 1)
tW
-
2 80 - - 100 - 120 -
ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Set-up Time Data to Clock
(Figure 5)
tSU
- 2 60 - - 75 - 70 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Hold Time, Data to Clock
tH
-
2 3-
-
3
-
3
- ns
(Figure 5)
4.5 3 -
-
3
-
3
- ns
6 3-
-
3
-
3
- ns
Removal Time, MR to Clock
tREM
- 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
HCT TYPES
Maximum Clock Frequency
(Figure 2)
fMAX
- 4.5 25 - - 20 - 16 - MHz
MR Pulse Width
(Figure 2)
tw - 4.5 12 - - 15 - 18 - ns
Clock Pulse Width (Figure 2)
Set-up Time Data to Clock
(Figure 6)
Hold Time, Data to Clock
(Figure 6)
Removal Time, MR to Clock
tw
tSU
tH
tREM
- 4.5 20 - - 25 - 30 - ns
- 4.5 12 - - 15 - 18 - ns
-
4.5 3 -
-
3
-
3
- ns
- 4.5 10 - - 13 - 15 - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay,
Clock to Output
(Figure 3)
TEST
SYMBOL CONDITIONS VCC (V)
tPLH, tPHL CL = 50pF
2
4.5
6
25oC
-40oC TO 85oC
TYP MAX
MAX
- 150
- 30
- 26
190
38
30
-55oC TO
125oC
MAX
225
45
38
UNITS
ns
ns
ns
Propagation Delay,
MR to Output
(Figure 3)
tPHL
CL = 15pF
CL = 50pF
5 12 -
2 - 150
4.5 - 30
6 - 26
-
190
38
30
- ns
225 ns
45 ns
38 ns
Output Transition Time
tTLH, tTHL CL = 50pF
2
- 75
(Figure 3)
4.5 - 15
95
19
110 ns
22 ns
6 - 13
16
19 ns
Input Capacitance
Maximum Clock Frequency
CI
fMAX
-
CL = 15pF
- - 10
5 60 -
10
-
10 pF
- MHz
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 54HCT273.PDF ] | |
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