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PDF IDT72V275 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V275 | |
| Descripción | (IDT72V275 / IDT72V285) 3.3 VOLT CMOS SuperSync FIFO | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT CMOS SuperSync FIFO™
32,768 X 18
65,536 X 18
IDT72V275
IDT72V285
.EATURES:
• Choose among the following memory organizations:
IDT72V275
32,768 x 18
IDT72V285
65,536 x 18
• Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
DESCRIPTION:
The IDT72V275/72V285 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data.
DataShee
.UNCTIONAL BLOCK DIAGRAM DataSheet4U.com
WEN WCLK
D0 -D17
LD SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
32,768 x 18
65,536 x 18
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
MRS
PRS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RCLK
REN
Q0 -Q17
OE
DataSheeStu4peUrS.ycnocFmIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2001 Integrated Device Technology, Inc.
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4512 drw 01
APRIL 2001
DSC-4512/1
1 page  
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IDT72V275/72V285
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Commercial
VTERM
Terminal Voltage
with respect to GND
–0.5 to +4.6
TSTG Storage
Temperature
–55 to +125
IOUT DC Output Current –50 to +50
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ. Max.
VCC Supply Voltage(Com’l & Ind’l) 3.0 3.3
3.6
GND Supply Voltage(Com’l & Ind’l) 0
0
0
VIH Input High Voltage
(Com’l & Ind’l)
VIL(1) Input Low Voltage
(Com’l & Ind’l)
2.0 — VCC + 0.5
— — 0.8
TA OperatingTemperature
Commercial
0 — 70
TA OperatingTemperature
-40
Industrial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
85
Unit
V
V
V
V
oC
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
et4U.com Symbol
Parameter
IDT72V275L
IDT72V285L
Com’’l & Ind’l (1)
tCLK = 10, 15, 20 ns
Min. Max.
Unit DataShee
ILI(2) InputLeakageCurrent
ILO(3) OutputLeakageCurrent
DataSheet4U.com
–1
–10
1 µA
10 µA
VOH
VOL
ICC1(4,5,6)
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
2.4 — V
— 0.4 V
— 60 mA
ICC2(4,7)
NOTES:
Standby Current
— 20 mA
1. Industrial temperature range product for the 15ns is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 11 + 1.65*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25oC, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL
= capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol
CIN(2)
COUT(1,2)
Parameter(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
10
10
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
DataSheet4U.com
DataSheet4 U .com
Unit
pF
pF
5
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IDT72V275/72V285
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
REN and WEN must be HIGH before bringing RT LOW.
INPUTS:
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
DATA IN (D0 - D17)
noticeable if EF was HIGH before setup. During this period, the internal
Data inputs for 18-bit wide data.
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to
a LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array. PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH.
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for
the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold
127 words from the empty boundary and PAF is assigned a threshold 127
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
words from the full boundary; 127 words corresponds to an offset value of Mode), for the relevant timing diagram.
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
If LD is HIGH during Master Reset, then PAE is assigned a threshold
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
1,023 words from the empty boundary and PAF is assigned a threshold input determines whether the device will operate in IDT Standard mode or First
1,023 words from the full boundary; 1,023 words corresponds to an offset Word Fall Through (FWFT) mode.
value of 3FFH. Following Master Reset, serial loading of the offsets is If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
et4U.compermitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
mode will be selected.
whether or not there are
This mode uses the Empty Flag (EF)
any words present in the FIFO memory.
to indicate
It also uses
DataShee
describing the LD pin for further details.)
DataSheett4hUe F.cuoll mFlag function (FF) to indicate whether or not the FIFO memory has
During a Master Reset, the output register is initialized to all zeroes. A any free space for writing. In IDT Standard mode, every word read from the
Master Reset is required after power up, before a write operation can take FIFO, including the first, must be requested using the Read Enable (REN)
place. MRS is asynchronous.
and RCLK.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges, REN = LOW is not necessary. Subse-
quent words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle,
the FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HFflag to LOW.) The Write and Read Clocks can either
be independent or coincident.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
DataSheecmto4enmUsios.rtcsyo.omf reading out the memory contents, starting at the beginning of the
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
11
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