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PDF LCX541 Data sheet ( Hoja de datos )
| Número de pieza | LCX541 | |
| Descripción | 74LCX541 | |
| Fabricantes | ETC | |
| Logotipo |  |
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March 1995
Revised April 1999
www.DataSheet4U.com
74LCX541
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
General Description
The LCX541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers. The LCX541 is a
non inverting option of the LCX540.
This device is similar in function to the LCX244 while pro-
viding flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
The LCX541 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal
environment. The LCX541 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.
Features
s 5V tolerant input and outputs
s 2.3V–3.6V VCC specifications provided
s 6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/ EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down,
OE should be tied to VCC through a pull-up resistor: the minimum value
or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX541WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LCX541SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX541MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012404.prf
www.fairchildsemi.com
1 page  
AC Loading and Waveforms Generic for LCX Family
www.DataSheet4U.com
FIGURE 1. AC Test Circuit
(CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH,tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and
Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f=1MHz, tr=tf=3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LCX541.PDF ] | |
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