PDF HYMD564646CP6 Data sheet ( Hoja de datos )

Número de pieza	HYMD564646CP6
Descripción	184Pin Unbuffered DDR SDRAM DIMMs
Fabricantes	Hynix
Logotipo
Hay una vista previa y un enlace de descarga de HYMD564646CP6 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! www.DataSheet4U.com 184pin Unbuffered DDR SDRAM DIMMs based on 512Mb C ver. (TSOP) This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR SDRAMs in 400mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb C ver. based unbuffered DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC Standard 184-pin dual in-line memory module (DIMM) • Two ranks 128M x 72, 128M x 64 and One rank 64M x 72, 64M x 64, 32M x 64 organization • 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400, 2.5V ± 0.2V for DDR333 and below • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock operations (CK & /CK) with 133/166/200MHz • DLL aligns DQ and DQS transition with CK transition • Programmable CAS Latency: DDR266(2, 2.5 clock), DDR333(2.5 clock), DDR400(3 clock) • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Edge-aligned DQS with data outs and Center-aligned DQS with data inputs • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial Presence Detect (SPD) with EEPROM • Built with 512Mb DDR SDRAMs in 400 mil TSOP II packages • All lead-free products (RoHS compliant) ADDRESS TABLE Organization Ranks 256MB 512MB 512MB 1GB 1GB 32M x 64 64M x 64 64M x 72 128M x 64 128M x 72 1 1 1 2 2 DataSheet4U.com SDRAMs 32Mb x 16 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) PERFORMANCE RANGE Part-Number Suffix Speed Bin CL - tRCD- tRP Max Clock Frequency CL=3 CL=2.5 CL=2 -D431 DDR400B 3-3-3 200 166 133 -J DDR333 2.5-3-3 - 166 133 -H DDR266B 2.5-3-3 - 133 133 Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms Unit - CK MHz MHz MHz Note: 1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below DataShee This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Nov. 2005 1 DataSheet4U.com DataSheet4 U .com DataSheet4U.com 1 page www.DataSheet4U.com et4U.com 11 184pin Unbuffered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J] DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CS0 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D0 DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D4 DQS1 DM1/DQS10 DDQQ89 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D1 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D5 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D2 DQS6 DM6/DQS15 DataSheet4U.com DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D6 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D3 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D7 SCL Serial PD W P A0 A1 A2 SA0 SA1 SA2 VDD SPD SDA VDD /VDDQ VREF VSS VDDID BA0-BA1 A0-A13 /RAS /CAS CKE0 /WE BA0-BA1 : SDRAMs D0-D7 A0-A13 : SDRAMs D0-D7 /RAS : SDRAMs D0-D7 /CAS : SDRAMs D0-D7 CKE : SDRAMs D0-D7 /WE : SDRAMs D0-D7 SPD DO-D7 Clock Wiring Clock Input SDRAMs DO-D7 DO-D7 CK0, /CK0 CK1, /CK1 CK2, /CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs Strap:see Note 4 Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ≠ V DDQ 5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5% DataShee Rev. 1.2 / Nov. 2005 DataSheet4U.com DataSheet4 U .com DataSheet4U.com 5 5 Page www.DataSheet4U.com et4U.com 11 184pin Unbuffered DDR SDRAM DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J] Symbol IDD0 IDD1 IDD2P IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 Test Condition DDR400B One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1040 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 1360 All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active ; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 1680 Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per 1840 clock cycle DataSheet4U.com tRC=tRFC(min) - 8tCK for DDR200 at 100Mhz, 10tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 2080 CKE=<0.2V; External clock on; tCK =tCK(min) Normal Low Power Four bank interleaving with BL=4 Refer to the following page for detailed test condition 2880 Speed DDR333 960 1200 80 280 360 480 1520 1680 1920 40 20 2800 DDR266B 800 960 1360 1440 1760 2720 Unit mA mA mA mA mA mA mA mA mA mA mA mA Note DataShee Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.2 / Nov. 2005 DataSheet4U.com DataSheet4 U .com DataSheet4U.com 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet HYMD564646CP6.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HYMD564646CP6	184Pin Unbuffered DDR SDRAM DIMMs	Hynix
HYMD564646CP6J	184Pin Unbuffered DDR SDRAM DIMMs	Hynix
HYMD564646CP8	184Pin Unbuffered DDR SDRAM DIMMs	Hynix
HYMD564646CP8J	184Pin Unbuffered DDR SDRAM DIMMs	Hynix

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar