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PDF AD7760 Data sheet ( Hoja de datos )
| Número de pieza | AD7760 | |
| Descripción | 2.5 MSPS 20-Bit ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2.5 MSPS, 20-Bit Σ∆ ADC
Preliminary Technical Data
AD7760
FEATURES
High performance 20-bit Sigma-Delta ADC
118dB SNR at 78kHz output data rate
100dB SNR at 2.5MHz output data rate
2.5 MHz maximum fully filtered output word rate
Programmable over-sampling rate (8x to 256x)
Flexible parallel interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low pass FIR filter with default or user programmable
coefficients
Over-range alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power down modes
Synchronization of multiple devices via SYNC pin
VREF+
MCLK
MCLK
SYNC
RESET
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
DataSheet4U.com
FUNCTIONAL BLOCK DIAGRAM
VIN- VIN+
+
BUF
-
DIFF
AD7760
Control Logic,
I/O and
Registers
Multi-Bit
Sigma-Delta
Modulator
Reconstruction
Programmable
Decimation
FIR Filter
Engine
AVDD1
AVDD2
AVDD3
AVDD4
DECAP
RBIAS
AGND
VDRIVE
DVDD
DGND
DB0 - DB15
Figure 1.
DataShee
PRODUCT OVERVIEW
The AD7760 high performance 20-bit sigma delta analog to
digital converter combines wide input bandwidth and high
speed with the benefits of sigma delta conversion with
performance of 100dB SNR at 2.5MSPS making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced anti-aliasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
over-range flag, internal gain & offset registers and a low-pass
digital FIR filter make the AD7760 a compact highly integrated
data acquisition device requiring minimal peripheral
component selection. In addition the device offers
programmable decimation rates and the digital FIR filter can be
adjusted if the default characteristics are not appropriate to the
application. The AD7760 is ideal for applications demanding
high SNR without necessitating design of complex front end
signal processing.
The differential input is sampled at up to 40MS/s by an analog
modulator. The modulator output is processed by a series of
low-pass filters, the final one having default or user
programmable coefficients. The sample rate, filter corner
frequencies and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7760.
The reference voltage supplied to the AD7760 determines the
analog input range. With a 4V reference, the analog input range
is ±3.2V differential biased around a common mode of 2V. This
common mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.
The AD7760 is available in an exposed paddle 64-lead TQFP
and 48-lead CSP packages and is specified over the industrial
temperature range from -40°C to +85°C.
Rev. PrN
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
DataSheet4Uinf.rcinogemments of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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Preliminary Technical Data
AD7760
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TIMING SPECIFICATIONS
Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted
Parameter
fMCLK
fICLK
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
Limit at TMIN, TMAX
12.288
80
12.288
20
0.5 × tICLK
10
2
10
tICLK
tICLK
2
10
0.5 × tICLK
0.5 × tICLK
15
TBD
TBD
10
tICLK
tICLK
10
10
Unit Description
MHz min
Applied Master Clock Frequency
MHz max
MHz min
Internal Modulator Clock Derived from MCLK.
MHz max
typ DRDY Pulse Width
nS min
DRDY Falling Edge to CS falling Edge
nS min
RD/WR Setup Time to CS Falling Edge
nS typ
Data Access Time
min CS Low Pulse Width
min CS High Pulse Width Between Reads
nS min
RD/WR Hold Time to CS Rising Edge
nS max
Bus Relinquish Time
typ DRDY High Period
typ DRDY Low Period
nS typ
Data Access Time
xS min
Data Valid Prior to DRDY Rising Edge
xS min
Data Valid After DRDY Rising Edge
nS max
Bus Relinquish Time
xS min
CS Low Pulse Width
xS min DataCSShHeiegth4PUe.rcioodmBetween Address and Data
nS min
Data Setup Time
nS min
Data Hold Time
DataShee
1 tICLK = 1/fICLK
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Rev. PrN | Page 5 of 22
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Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: TA = 25°C, TBD, unless otherwise noted.
AD7760
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Figure 7. TBD
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ALL CAPS ( Init ial cap)
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Figure 11. TBD
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Figure 12. TBD
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Rev. PrN | Page 11 of 22
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| PDF Descargar | [ Datasheet AD7760.PDF ] | |
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